Add CHANGELOG entry

diff --git a/CHANGELOG b/CHANGELOG
index ca42df71e56b9d534e0e0dfe90ea03c21f89a977..92456df99b610a1155ecd3cce76e3ae032849df1 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "opt_share" pass, run as part of "opt -full"
     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
     - Removed "ice40_unlut"
+    - Added "xilinx_srl" for Xilinx shift register extraction
+    - Removed "shregmap -tech xilinx"
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------