xilinx: Add simulation models for MULT18X18* and DSP48A*.

This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 03985b1befccdf243c9d76b5088a5eef2103d7b7..5faddcd523af0e76100129e44ed079db83e6c847 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -581,6 +581,515 @@ module SRLC32E (
   endgenerate
 endmodule
 
+// DSP
+
+// Virtex 2, Virtex 2 Pro, Spartan 3.
+
+// Asynchronous mode.
+
+module MULT18X18 (
+    input signed [17:0] A,
+    input signed [17:0] B,
+    output signed [35:0] P
+);
+
+assign P = A * B;
+
+endmodule
+
+// Synchronous mode.
+
+module MULT18X18S (
+    input signed [17:0] A,
+    input signed [17:0] B,
+    output reg signed [35:0] P,
+    (* clkbuf_sink *)
+    input C,
+    input CE,
+    input R
+);
+
+always @(posedge C)
+       if (R)
+               P <= 0;
+       else if (CE)
+               P <= A * B;
+
+endmodule
+
+// Spartan 3E, Spartan 3A.
+
+module MULT18X18SIO (
+    input signed [17:0] A,
+    input signed [17:0] B,
+    output signed [35:0] P,
+    (* clkbuf_sink *)
+    input CLK,
+    input CEA,
+    input CEB,
+    input CEP,
+    input RSTA,
+    input RSTB,
+    input RSTP,
+    input signed [17:0] BCIN,
+    output signed [17:0] BCOUT
+);
+
+parameter integer AREG = 1;
+parameter integer BREG = 1;
+parameter B_INPUT = "DIRECT";
+parameter integer PREG = 1;
+
+// The multiplier.
+wire signed [35:0] P_MULT;
+assign P_MULT = A_MULT * B_MULT;
+
+// The cascade output.
+assign BCOUT = B_MULT;
+
+// The B input multiplexer.
+wire signed [17:0] B_MUX;
+assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN;
+
+// The registers.
+reg signed [17:0] A_REG;
+reg signed [17:0] B_REG;
+reg signed [35:0] P_REG;
+
+initial begin
+       A_REG = 0;
+       B_REG = 0;
+       P_REG = 0;
+end
+
+always @(posedge CLK) begin
+       if (RSTA)
+               A_REG <= 0;
+       else if (CEA)
+               A_REG <= A;
+
+       if (RSTB)
+               B_REG <= 0;
+       else if (CEB)
+               B_REG <= B_MUX;
+
+       if (RSTP)
+               P_REG <= 0;
+       else if (CEP)
+               P_REG <= P_MULT;
+end
+
+// The register enables.
+wire signed [17:0] A_MULT;
+wire signed [17:0] B_MULT;
+assign A_MULT = (AREG == 1) ? A_REG : A;
+assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
+assign P = (PREG == 1) ? P_REG : P_MULT;
+
+endmodule
+
+// Spartan 3A DSP.
+
+module DSP48A (
+    input signed [17:0] A,
+    input signed [17:0] B,
+    input signed [47:0] C,
+    input signed [17:0] D,
+    input signed [47:0] PCIN,
+    input CARRYIN,
+    input [7:0] OPMODE,
+    output signed [47:0] P,
+    output signed [17:0] BCOUT,
+    output signed [47:0] PCOUT,
+    output CARRYOUT,
+    (* clkbuf_sink *)
+    input CLK,
+    input CEA,
+    input CEB,
+    input CEC,
+    input CED,
+    input CEM,
+    input CECARRYIN,
+    input CEOPMODE,
+    input CEP,
+    input RSTA,
+    input RSTB,
+    input RSTC,
+    input RSTD,
+    input RSTM,
+    input RSTCARRYIN,
+    input RSTOPMODE,
+    input RSTP
+);
+
+parameter integer A0REG = 0;
+parameter integer A1REG = 1;
+parameter integer B0REG = 0;
+parameter integer B1REG = 1;
+parameter integer CREG = 1;
+parameter integer DREG = 1;
+parameter integer MREG = 1;
+parameter integer CARRYINREG = 1;
+parameter integer OPMODEREG = 1;
+parameter integer PREG = 1;
+parameter CARRYINSEL = "CARRYIN";
+parameter RSTTYPE = "SYNC";
+
+// This is a strict subset of Spartan 6 -- reuse its model.
+
+DSP48A1 #(
+       .A0REG(A0REG),
+       .A1REG(A1REG),
+       .B0REG(B0REG),
+       .B1REG(B1REG),
+       .CREG(CREG),
+       .DREG(DREG),
+       .MREG(MREG),
+       .CARRYINREG(CARRYINREG),
+       .CARRYOUTREG(0),
+       .OPMODEREG(OPMODEREG),
+       .PREG(PREG),
+       .CARRYINSEL(CARRYINSEL),
+       .RSTTYPE(RSTTYPE)
+) upgrade (
+       .A(A),
+       .B(B),
+       .C(C),
+       .D(D),
+       .PCIN(PCIN),
+       .CARRYIN(CARRYIN),
+       .OPMODE(OPMODE),
+       // M unconnected
+       .P(P),
+       .BCOUT(BCOUT),
+       .PCOUT(PCOUT),
+       .CARRYOUT(CARRYOUT),
+       // CARRYOUTF unconnected
+       .CLK(CLK),
+       .CEA(CEA),
+       .CEB(CEB),
+       .CEC(CEC),
+       .CED(CED),
+       .CEM(CEM),
+       .CECARRYIN(CECARRYIN),
+       .CEOPMODE(CEOPMODE),
+       .CEP(CEP),
+       .RSTA(RSTA),
+       .RSTB(RSTB),
+       .RSTC(RSTC),
+       .RSTD(RSTD),
+       .RSTM(RSTM),
+       .RSTCARRYIN(RSTCARRYIN),
+       .RSTOPMODE(RSTOPMODE),
+       .RSTP(RSTP)
+);
+
+endmodule
+
+// Spartan 6.
+
+module DSP48A1 (
+    input signed [17:0] A,
+    input signed [17:0] B,
+    input signed [47:0] C,
+    input signed [17:0] D,
+    input signed [47:0] PCIN,
+    input CARRYIN,
+    input [7:0] OPMODE,
+    output signed [35:0] M,
+    output signed [47:0] P,
+    output signed [17:0] BCOUT,
+    output signed [47:0] PCOUT,
+    output CARRYOUT,
+    output CARRYOUTF,
+    (* clkbuf_sink *)
+    input CLK,
+    input CEA,
+    input CEB,
+    input CEC,
+    input CED,
+    input CEM,
+    input CECARRYIN,
+    input CEOPMODE,
+    input CEP,
+    input RSTA,
+    input RSTB,
+    input RSTC,
+    input RSTD,
+    input RSTM,
+    input RSTCARRYIN,
+    input RSTOPMODE,
+    input RSTP
+);
+
+parameter integer A0REG = 0;
+parameter integer A1REG = 1;
+parameter integer B0REG = 0;
+parameter integer B1REG = 1;
+parameter integer CREG = 1;
+parameter integer DREG = 1;
+parameter integer MREG = 1;
+parameter integer CARRYINREG = 1;
+parameter integer CARRYOUTREG = 1;
+parameter integer OPMODEREG = 1;
+parameter integer PREG = 1;
+parameter CARRYINSEL = "OPMODE5";
+parameter RSTTYPE = "SYNC";
+
+wire signed [35:0] M_MULT;
+wire signed [47:0] P_IN;
+wire signed [17:0] A0_OUT;
+wire signed [17:0] B0_OUT;
+wire signed [17:0] A1_OUT;
+wire signed [17:0] B1_OUT;
+wire signed [17:0] B1_IN;
+wire signed [47:0] C_OUT;
+wire signed [17:0] D_OUT;
+wire signed [7:0] OPMODE_OUT;
+wire CARRYIN_OUT;
+wire CARRYOUT_IN;
+wire CARRYIN_IN;
+reg signed [47:0] XMUX;
+reg signed [47:0] ZMUX;
+
+// The registers.
+reg signed [17:0] A0_REG;
+reg signed [17:0] A1_REG;
+reg signed [17:0] B0_REG;
+reg signed [17:0] B1_REG;
+reg signed [47:0] C_REG;
+reg signed [17:0] D_REG;
+reg signed [35:0] M_REG;
+reg signed [47:0] P_REG;
+reg [7:0] OPMODE_REG;
+reg CARRYIN_REG;
+reg CARRYOUT_REG;
+
+initial begin
+       A0_REG = 0;
+       A1_REG = 0;
+       B0_REG = 0;
+       B1_REG = 0;
+       C_REG = 0;
+       D_REG = 0;
+       M_REG = 0;
+       P_REG = 0;
+       OPMODE_REG = 0;
+       CARRYIN_REG = 0;
+       CARRYOUT_REG = 0;
+end
+
+generate
+
+if (RSTTYPE == "SYNC") begin
+       always @(posedge CLK) begin
+               if (RSTA) begin
+                       A0_REG <= 0;
+                       A1_REG <= 0;
+               end else if (CEA) begin
+                       A0_REG <= A;
+                       A1_REG <= A0_OUT;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTB) begin
+                       B0_REG <= 0;
+                       B1_REG <= 0;
+               end else if (CEB) begin
+                       B0_REG <= B;
+                       B1_REG <= B1_IN;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTC) begin
+                       C_REG <= 0;
+               end else if (CEC) begin
+                       C_REG <= C;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTD) begin
+                       D_REG <= 0;
+               end else if (CED) begin
+                       D_REG <= D;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTM) begin
+                       M_REG <= 0;
+               end else if (CEM) begin
+                       M_REG <= M_MULT;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTP) begin
+                       P_REG <= 0;
+               end else if (CEP) begin
+                       P_REG <= P_IN;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTOPMODE) begin
+                       OPMODE_REG <= 0;
+               end else if (CEOPMODE) begin
+                       OPMODE_REG <= OPMODE;
+               end
+       end
+
+       always @(posedge CLK) begin
+               if (RSTCARRYIN) begin
+                       CARRYIN_REG <= 0;
+                       CARRYOUT_REG <= 0;
+               end else if (CECARRYIN) begin
+                       CARRYIN_REG <= CARRYIN_IN;
+                       CARRYOUT_REG <= CARRYOUT_IN;
+               end
+       end
+end else begin
+       always @(posedge CLK, posedge RSTA) begin
+               if (RSTA) begin
+                       A0_REG <= 0;
+                       A1_REG <= 0;
+               end else if (CEA) begin
+                       A0_REG <= A;
+                       A1_REG <= A0_OUT;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTB) begin
+               if (RSTB) begin
+                       B0_REG <= 0;
+                       B1_REG <= 0;
+               end else if (CEB) begin
+                       B0_REG <= B;
+                       B1_REG <= B1_IN;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTC) begin
+               if (RSTC) begin
+                       C_REG <= 0;
+               end else if (CEC) begin
+                       C_REG <= C;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTD) begin
+               if (RSTD) begin
+                       D_REG <= 0;
+               end else if (CED) begin
+                       D_REG <= D;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTM) begin
+               if (RSTM) begin
+                       M_REG <= 0;
+               end else if (CEM) begin
+                       M_REG <= M_MULT;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTP) begin
+               if (RSTP) begin
+                       P_REG <= 0;
+               end else if (CEP) begin
+                       P_REG <= P_IN;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTOPMODE) begin
+               if (RSTOPMODE) begin
+                       OPMODE_REG <= 0;
+               end else if (CEOPMODE) begin
+                       OPMODE_REG <= OPMODE;
+               end
+       end
+
+       always @(posedge CLK, posedge RSTCARRYIN) begin
+               if (RSTCARRYIN) begin
+                       CARRYIN_REG <= 0;
+                       CARRYOUT_REG <= 0;
+               end else if (CECARRYIN) begin
+                       CARRYIN_REG <= CARRYIN_IN;
+                       CARRYOUT_REG <= CARRYOUT_IN;
+               end
+       end
+end
+
+endgenerate
+
+// The register enables.
+assign A0_OUT = (A0REG == 1) ? A0_REG : A;
+assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT;
+assign B0_OUT = (B0REG == 1) ? B0_REG : B;
+assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN;
+assign C_OUT = (CREG == 1) ? C_REG : C;
+assign D_OUT = (DREG == 1) ? D_REG : D;
+assign M = (MREG == 1) ? M_REG : M_MULT;
+assign P = (PREG == 1) ? P_REG : P_IN;
+assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE;
+assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN;
+assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN;
+assign CARRYOUTF = CARRYOUT;
+
+// The pre-adder.
+wire signed [17:0] PREADDER;
+assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT;
+assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT;
+
+// The multiplier.
+assign M_MULT = A1_OUT * B1_OUT;
+
+// The carry in selection.
+assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN;
+
+// The post-adder inputs.
+always @* begin
+       case (OPMODE_OUT[1:0])
+               2'b00: XMUX <= 0;
+               2'b01: XMUX <= M;
+               2'b10: XMUX <= P;
+               2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT};
+               default: XMUX <= 48'hxxxxxxxxxxxx;
+       endcase
+end
+
+always @* begin
+       case (OPMODE_OUT[3:2])
+               2'b00: ZMUX <= 0;
+               2'b01: ZMUX <= PCIN;
+               2'b10: ZMUX <= P;
+               2'b11: ZMUX <= C_OUT;
+               default: ZMUX <= 48'hxxxxxxxxxxxx;
+       endcase
+end
+
+// The post-adder.
+wire signed [48:0] X_EXT;
+wire signed [48:0] Z_EXT;
+assign X_EXT = XMUX;
+assign Z_EXT = ZMUX;
+assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT);
+
+// Cascade outputs.
+assign BCOUT = B1_OUT;
+assign PCOUT = P;
+
+endmodule
+
+// TODO: DSP48 (Virtex 4).
+
+// TODO: DSP48E (Virtex 5).
+
+// Virtex 6, Series 7.
+
 module DSP48E1 (
     output [29:0] ACOUT,
     output [17:0] BCOUT,
@@ -1043,3 +1552,5 @@ module DSP48E1 (
     endgenerate
 
 endmodule
+
+// TODO: DSP48E2 (Ultrascale).

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index ef7ce856adf77c42a7c9dc5c5a235542f7fc96b9..f401ebe7817875dcd57e7f181683094fb1a88771 100644 (file)
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -204,11 +204,11 @@ CELLS = [
     Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
 
     # Multipliers and DSP.
-    Cell('MULT18X18'), # Spartan 3
-    Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3
-    Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
-    Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
-    Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
+    # Cell('MULT18X18'), # Virtex 2, Spartan 3
+    # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3
+    # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
+    # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
+    # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
     Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4
     Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5
     #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 72a3b6cbb18de1ea0d570781214973176d464b4d..ce0949f2cbc7bb8866c93d6d76a03ddc0f7a464e 100644 (file)
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -6218,133 +6218,6 @@ module URAM288_BASE (...);
     input SLEEP;
 endmodule
 
-module MULT18X18 (...);
-    output [35:0] P;
-    input [17:0] A;
-    input [17:0] B;
-endmodule
-
-module MULT18X18S (...);
-    output [35:0] P;
-    input [17:0] A;
-    input [17:0] B;
-    (* clkbuf_sink *)
-    input C;
-    input CE;
-    input R;
-endmodule
-
-module MULT18X18SIO (...);
-    parameter integer AREG = 1;
-    parameter integer BREG = 1;
-    parameter B_INPUT = "DIRECT";
-    parameter integer PREG = 1;
-    output [17:0] BCOUT;
-    output [35:0] P;
-    input [17:0] A;
-    input [17:0] B;
-    input [17:0] BCIN;
-    input CEA;
-    input CEB;
-    input CEP;
-    (* clkbuf_sink *)
-    input CLK;
-    input RSTA;
-    input RSTB;
-    input RSTP;
-endmodule
-
-module DSP48A (...);
-    parameter integer A0REG = 0;
-    parameter integer A1REG = 1;
-    parameter integer B0REG = 0;
-    parameter integer B1REG = 1;
-    parameter integer CARRYINREG = 1;
-    parameter CARRYINSEL = "CARRYIN";
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer MREG = 1;
-    parameter integer OPMODEREG = 1;
-    parameter integer PREG = 1;
-    parameter RSTTYPE = "SYNC";
-    output [17:0] BCOUT;
-    output CARRYOUT;
-    output [47:0] P;
-    output [47:0] PCOUT;
-    input [17:0] A;
-    input [17:0] B;
-    input [47:0] C;
-    input CARRYIN;
-    input CEA;
-    input CEB;
-    input CEC;
-    input CECARRYIN;
-    input CED;
-    input CEM;
-    input CEOPMODE;
-    input CEP;
-    (* clkbuf_sink *)
-    input CLK;
-    input [17:0] D;
-    input [7:0] OPMODE;
-    input [47:0] PCIN;
-    input RSTA;
-    input RSTB;
-    input RSTC;
-    input RSTCARRYIN;
-    input RSTD;
-    input RSTM;
-    input RSTOPMODE;
-    input RSTP;
-endmodule
-
-module DSP48A1 (...);
-    parameter integer A0REG = 0;
-    parameter integer A1REG = 1;
-    parameter integer B0REG = 0;
-    parameter integer B1REG = 1;
-    parameter integer CARRYINREG = 1;
-    parameter integer CARRYOUTREG = 1;
-    parameter CARRYINSEL = "OPMODE5";
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer MREG = 1;
-    parameter integer OPMODEREG = 1;
-    parameter integer PREG = 1;
-    parameter RSTTYPE = "SYNC";
-    output [17:0] BCOUT;
-    output CARRYOUT;
-    output CARRYOUTF;
-    output [35:0] M;
-    output [47:0] P;
-    output [47:0] PCOUT;
-    input [17:0] A;
-    input [17:0] B;
-    input [47:0] C;
-    input CARRYIN;
-    input CEA;
-    input CEB;
-    input CEC;
-    input CECARRYIN;
-    input CED;
-    input CEM;
-    input CEOPMODE;
-    input CEP;
-    (* clkbuf_sink *)
-    input CLK;
-    input [17:0] D;
-    input [7:0] OPMODE;
-    input [47:0] PCIN;
-    input RSTA;
-    input RSTB;
-    input RSTC;
-    input RSTCARRYIN;
-    input RSTD;
-    input RSTM;
-    input RSTOPMODE;
-    input RSTP;
-endmodule
-
 module DSP48 (...);
     parameter integer AREG = 1;
     parameter integer BREG = 1;