---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 11837684 # Number of BTB hits
-global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted
-global.BPredUnit.lookups 17533197 # Number of BP lookups
-global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target.
-host_inst_rate 57997 # Simulator instruction rate (inst/s)
-host_mem_usage 178748 # Number of bytes of host memory used
-host_seconds 1423.90 # Real time elapsed on the host
-host_tick_rate 73521 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 12030516 # Number of BTB hits
+global.BPredUnit.BTBLookups 15440177 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1230 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 2016046 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 13150093 # Number of conditional branches predicted
+global.BPredUnit.lookups 17791196 # Number of BP lookups
+global.BPredUnit.usedRAS 1688779 # Number of times the RAS was used to get a target.
+host_inst_rate 79686 # Simulator instruction rate (inst/s)
+host_mem_usage 157864 # Number of bytes of host memory used
+host_seconds 1056.39 # Real time elapsed on the host
+host_tick_rate 100832 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 10465878 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 3573806 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 29942981 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 9492949 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 82582323 # Number of instructions simulated
-sim_seconds 0.000105 # Number of seconds simulated
-sim_ticks 104686099 # Number of ticks simulated
-system.cpu.commit.COM:branches 10071057 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached
+sim_insts 84179641 # Number of instructions simulated
+sim_seconds 0.000107 # Number of seconds simulated
+sim_ticks 106518101 # Number of ticks simulated
+system.cpu.commit.COM:branches 10240671 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3286550 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 65490840
+system.cpu.commit.COM:committed_per_cycle.samples 66541371
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 32034998 4891.52%
- 1 13785472 2104.95%
- 2 8057025 1230.25%
- 3 3669149 560.25%
- 4 1988059 303.56%
- 5 1377349 210.31%
- 6 785420 119.93%
- 7 617467 94.28%
- 8 3175901 484.94%
+ 0 32590645 4897.80%
+ 1 14052557 2111.85%
+ 2 7925597 1191.08%
+ 3 3833922 576.17%
+ 4 2055997 308.98%
+ 5 1406670 211.40%
+ 6 778313 116.97%
+ 7 611120 91.84%
+ 8 3286550 493.91%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 90187947 # Number of instructions committed
-system.cpu.commit.COM:loads 19613586 # Number of loads committed
+system.cpu.commit.COM:count 91902973 # Number of instructions committed
+system.cpu.commit.COM:loads 20034401 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 25981086 # Number of memory references committed
+system.cpu.commit.COM:refs 26537088 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 82582323 # Number of Instructions Simulated
-system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated
-system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles
+system.cpu.commit.branchMispredicts 2003600 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 91902973 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 40960562 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 84179641 # Number of Instructions Simulated
+system.cpu.committedInsts_total 84179641 # Number of Instructions Simulated
+system.cpu.cpi 1.265367 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.265367 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 23044516 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5485.308046 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4904.691383 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23043646 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4772218 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 870 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 371 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2447441 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_mshr_misses 499 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501095 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4881.036474 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.310702 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6495173 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 28905498 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5922 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 4184 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 7957104 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3119.926690 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13204.657577 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 873 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2723696 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 29545611 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4958.438751 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29538819 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 33677716 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 6792 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 4555 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10404545 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29033347 # number of overall hits
-system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 6013 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses
+system.cpu.dcache.overall_accesses 29545611 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4958.438751 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 29538819 # number of overall hits
+system.cpu.dcache.overall_miss_latency 33677716 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 6792 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 4555 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10404545 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 104 # number of replacements
-system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 158 # number of replacements
+system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1401.371234 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29538819 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 75 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched
-system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 105 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 2237449 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12651 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 2840694 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 147924684 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 36686871 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 27530511 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 6274304 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45170 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 86541 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 17791196 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 17777552 # Number of cache lines fetched
+system.cpu.fetch.Cycles 46222210 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 487538 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 152510640 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2057778 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.244332 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 17777552 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 13719295 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.094475 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 71734044
+system.cpu.fetch.rateDist.samples 72815676
system.cpu.fetch.rateDist.min_value 0
- 0 43713095 6093.77%
- 1 2792314 389.26%
- 2 2129360 296.84%
- 3 3194083 445.27%
- 4 4028588 561.60%
- 5 1363321 190.05%
- 6 1870461 260.75%
- 7 1629807 227.20%
- 8 11013015 1535.26%
+ 0 44371798 6093.72%
+ 1 2823722 387.79%
+ 2 2124290 291.74%
+ 3 3251818 446.58%
+ 4 4141832 568.81%
+ 5 1395626 191.67%
+ 6 1928347 264.83%
+ 7 1658600 227.78%
+ 8 11119643 1527.09%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 17777552 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3389.584594 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2497.747914 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 17763934 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 46159363 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000766 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 13618 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3550 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25147326 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000566 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10068 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 3002.121212 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1764.395511 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 33 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 99070 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency
-system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses
-system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 17777552 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3389.584594 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency
+system.cpu.icache.demand_hits 17763934 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 46159363 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000766 # miss rate for demand accesses
+system.cpu.icache.demand_misses 13618 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3550 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25147326 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000566 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10068 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 17777552 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3389.584594 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 17495889 # number of overall hits
-system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses
-system.cpu.icache.overall_misses 13510 # number of overall misses
-system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses
+system.cpu.icache.overall_hits 17763934 # number of overall hits
+system.cpu.icache.overall_miss_latency 46159363 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000766 # miss rate for overall accesses
+system.cpu.icache.overall_misses 13618 # number of overall misses
+system.cpu.icache.overall_mshr_hits 3550 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25147326 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000566 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10068 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8115 # number of replacements
-system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8155 # number of replacements
+system.cpu.icache.sampled_refs 10068 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use
-system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1487.917031 # Cycle average of tags in use
+system.cpu.icache.total_refs 17763934 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12456785 # Number of branches executed
-system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate
-system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7006627 # Number of stores executed
+system.cpu.idleCycles 33702426 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12615755 # Number of branches executed
+system.cpu.iew.EXEC:nop 11674396 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.372220 # Inst execution rate
+system.cpu.iew.EXEC:refs 31504897 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7134544 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value
-system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back
+system.cpu.iew.WB:consumers 88896181 # num instructions consuming a value
+system.cpu.iew.WB:count 98303270 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.728803 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 63388475 # num instructions producing a value
-system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle
-system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 64787760 # num instructions producing a value
+system.cpu.iew.WB:rate 1.350029 # insts written-back per cycle
+system.cpu.iew.WB:sent 98915294 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2149664 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 135882 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 29942981 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2170747 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 9492949 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 132862510 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24370353 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2140113 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 99919134 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 28304 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 875 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 6274304 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 51812 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 9931 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 36041 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 935951 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2991 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 18493 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9874 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 9917218 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3003379 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 18493 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 19407 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9931 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 9908580 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2990262 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 19407 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 196546 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1953118 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.790285 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.790285 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 102059247 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 7 0.00% # Type of FU issued
- IntAlu 61666427 61.65% # Type of FU issued
- IntMult 468908 0.47% # Type of FU issued
+ IntAlu 62946758 61.68% # Type of FU issued
+ IntMult 472934 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2704055 2.70% # Type of FU issued
- FloatCmp 112834 0.11% # Type of FU issued
- FloatCvt 2307257 2.31% # Type of FU issued
- FloatMult 295394 0.30% # Type of FU issued
- FloatDiv 735688 0.74% # Type of FU issued
- FloatSqrt 122 0.00% # Type of FU issued
- MemRead 24586382 24.58% # Type of FU issued
- MemWrite 7149354 7.15% # Type of FU issued
+ FloatAdd 2777268 2.72% # Type of FU issued
+ FloatCmp 115533 0.11% # Type of FU issued
+ FloatCvt 2374854 2.33% # Type of FU issued
+ FloatMult 302376 0.30% # Type of FU issued
+ FloatDiv 755012 0.74% # Type of FU issued
+ FloatSqrt 321 0.00% # Type of FU issued
+ MemRead 24997637 24.49% # Type of FU issued
+ MemWrite 7316547 7.17% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1380880 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013530 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 195067 12.04% # attempts to use FU when none available
+ IntAlu 203697 14.75% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 1678 0.10% # attempts to use FU when none available
- FloatCmp 197 0.01% # attempts to use FU when none available
- FloatCvt 4552 0.28% # attempts to use FU when none available
- FloatMult 2392 0.15% # attempts to use FU when none available
- FloatDiv 951463 58.71% # attempts to use FU when none available
+ FloatAdd 1158 0.08% # attempts to use FU when none available
+ FloatCmp 74 0.01% # attempts to use FU when none available
+ FloatCvt 3812 0.28% # attempts to use FU when none available
+ FloatMult 2483 0.18% # attempts to use FU when none available
+ FloatDiv 669323 48.47% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 401417 24.77% # attempts to use FU when none available
- MemWrite 63978 3.95% # attempts to use FU when none available
+ MemRead 447537 32.41% # attempts to use FU when none available
+ MemWrite 52796 3.82% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044
+system.cpu.iq.ISSUE:issued_per_cycle.samples 72815676
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 28631398 3991.33%
- 1 15448994 2153.65%
- 2 12333631 1719.36%
- 3 7046540 982.31%
- 4 4503539 627.81%
- 5 2295007 319.93%
- 6 1113179 155.18%
- 7 291761 40.67%
- 8 69995 9.76%
+ 0 28801052 3955.34%
+ 1 15640626 2147.98%
+ 2 12881779 1769.09%
+ 3 7065095 970.27%
+ 4 4538706 623.31%
+ 5 2449165 336.35%
+ 6 1089108 149.57%
+ 7 276679 38.00%
+ 8 73466 10.09%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate
-system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits
+system.cpu.iq.ISSUE:rate 1.401611 # Inst issue rate
+system.cpu.iq.iqInstsAdded 121187678 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 102059247 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 36185843 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 120363 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 30311914 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 12304 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3854.841711 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2070.473487 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7231 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19555612 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.412305 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 5073 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10503512 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412305 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 5073 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.446087 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12304 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3854.841711 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7231 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19555612 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.412305 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5073 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10503512 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.412305 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5073 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 12409 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3854.841711 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7221 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4985 # number of overall misses
+system.cpu.l2cache.overall_hits 7336 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19555612 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.408816 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5073 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10503512 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.408816 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5073 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 5073 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3263.707979 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7336 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 71734044 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed
-system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 387 # Number of system calls
+system.cpu.numCycles 72815676 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 912182 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 68427307 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 427437 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 37674875 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 794086 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 185014418 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 143398786 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 105292951 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 26609827 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 6274304 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1283784 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 36865644 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 60704 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 3136689 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed
+system.cpu.timesIdled 10449 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 460435 # Simulator instruction rate (inst/s)
-host_mem_usage 178124 # Number of bytes of host memory used
-host_seconds 199.60 # Real time elapsed on the host
-host_tick_rate 765898 # Simulator tick rate (ticks/s)
+host_inst_rate 607322 # Simulator instruction rate (inst/s)
+host_mem_usage 157212 # Number of bytes of host memory used
+host_seconds 151.33 # Real time elapsed on the host
+host_tick_rate 1013960 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91900700 # Number of instructions simulated
+sim_insts 91903057 # Number of instructions simulated
sim_seconds 0.000153 # Number of seconds simulated
-sim_ticks 152870012 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 19995627 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3765.212314 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2765.212314 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19995156 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1773415 # number of ReadReq miss cycles
+sim_ticks 153438012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 471 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1302415 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 471 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6500813 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3867.178372 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2867.178372 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499204 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6222290 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000248 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1609 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4613290 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000248 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1609 # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12737.673077 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 26496440 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3844.088942 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494360 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7995705 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2080 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5915705 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2080 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 26496440 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3844.088942 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494360 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7995705 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2080 # number of overall misses
+system.cpu.dcache.overall_hits 26495079 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2222 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5915705 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2080 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 103 # number of replacements
-system.cpu.dcache.sampled_refs 2080 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 157 # number of replacements
+system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1399.324024 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26494360 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74 # number of writebacks
-system.cpu.icache.ReadReq_accesses 91900701 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3116.205529 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2116.205529 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 91892201 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 26487747 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000092 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 8500 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 17987747 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 8500 # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks 104 # number of writebacks
+system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 10810.847176 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 91900701 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3116.205529 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency
-system.cpu.icache.demand_hits 91892201 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 26487747 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000092 # miss rate for demand accesses
-system.cpu.icache.demand_misses 8500 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
+system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
+system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 17987747 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 8500 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 91900701 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3116.205529 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 91892201 # number of overall hits
-system.cpu.icache.overall_miss_latency 26487747 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000092 # miss rate for overall accesses
-system.cpu.icache.overall_misses 8500 # number of overall misses
+system.cpu.icache.overall_hits 91894548 # number of overall hits
+system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
+system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 17987747 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 8500 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 6677 # number of replacements
-system.cpu.icache.sampled_refs 8500 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 6681 # number of replacements
+system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1370.015418 # Cycle average of tags in use
-system.cpu.icache.total_refs 91892201 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use
+system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 10580 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2883.751500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1878.799057 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5912 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 13461352 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.441210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4668 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8770234 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.441210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4668 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 74 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.282348 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 10580 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2883.751500 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5912 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 13461352 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.441210 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4668 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 8770234 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.441210 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4668 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10654 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2883.751500 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5986 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 13461352 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.438145 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4668 # number of overall misses
+system.cpu.l2cache.overall_hits 6072 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4764 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 8770234 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.438145 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4668 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4668 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3056.777484 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 5986 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 152870012 # number of cpu cycles simulated
-system.cpu.num_insts 91900700 # Number of instructions executed
-system.cpu.num_refs 26536244 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 387 # Number of system calls
+system.cpu.numCycles 153438012 # number of cpu cycles simulated
+system.cpu.num_insts 91903057 # Number of instructions executed
+system.cpu.num_refs 26537109 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff