boards/targets/sim: fix

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 9c892911c614225ebb95f8e0cf6d58ba64b30946..0f0d657d06c045e2a419b20cf94d190e70fb706e 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -51,7 +51,7 @@ class BaseSoC(SoCSDRAM):
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,
                                 sdram_module.timing_settings,
-                                ControllerSettings(with_refresh=False))
+                                controller_settings=ControllerSettings(with_refresh=False))
             # reduce memtest size to speed up simulation
             self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
             self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)