(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index c61a03905085e91e27ed4e3373117681f1d0ca6a..eb59d1ecdbb19d1240eebec71b498e4ead3ee4ae 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -928,7 +928,8 @@ a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
 to support OpenCAPI properly? The answer is very likely to be yes.
 The saving grace here is that with
 the expectation of running only hot-loops with ZOLC-driven
-binaries, the size of L1 Cache needed would be miniscule compared
+binaries, the size of each PE's
+L1 Cache needed would be miniscule compared
 to the average high-end CPU.
 
 **Roadmap summary of Advanced SVP64**