mibuild: use SimpleCRG instead of CRG_SE, remove period parameter for CRG_DS, clean...

diff --git a/examples/cordic/cordic_impl.py b/examples/cordic/cordic_impl.py
index 9cc79194eacecc7472d2030d7b63648443fe20c7..d4c2e0663a02dc3681840310682aff2b264920cb 100644 (file)
--- a/examples/cordic/cordic_impl.py
+++ b/examples/cordic/cordic_impl.py
@@ -5,7 +5,8 @@ from migen.fhdl.std import *
 from migen.genlib.cordic import Cordic
 from mibuild.tools import mkdir_noerror
 from mibuild.generic_platform import *
-from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
+from mibuild.crg import SimpleCRG
+from mibuild.xilinx_ise import XilinxISEPlatform
 
 class CordicImpl(Module):
        def __init__(self, name, **kwargs):
@@ -38,7 +39,7 @@ class Platform(XilinxISEPlatform):
        ]
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
-                       lambda p: CRG_SE(p, "clk", "rst", 10.))
+                       lambda p: SimpleCRG(p, "clk", "rst"))
 
 if __name__ == "__main__":
        default = dict(width=16, guard=0, eval_mode="pipelined",

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index 24d0e8c2c41343c92c9299e6b48fb9962e6570f0..2a5e7a8d9a8ce9fd455a2c1f0d8657ba5d7f4318 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -5,14 +5,8 @@ import os, subprocess
 
 from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
-from mibuild.crg import SimpleCRG
 from mibuild import tools
 
-class CRG_SE(SimpleCRG):
-       def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
-               SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-               platform.add_period_constraint(platform, self.cd_sys.clk, period)
-
 def _format_constraint(c):
        if isinstance(c, Pins):
                return "set_location_assignment PIN_" + c.identifiers[0]

diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py
index b0906528de587c9bd2410caeac508abb0ba7f608..0fd93726bac2685418d5f869a1aae30b27c89b8c 100644 (file)
--- a/mibuild/platforms/de0nano.py
+++ b/mibuild/platforms/de0nano.py
@@ -2,7 +2,8 @@
 # License: BSD
 
 from mibuild.generic_platform import *
-from mibuild.altera_quartus import AlteraQuartusPlatform, CRG_SE
+from mibuild.crg import SimpleCRG
+from mibuild.altera_quartus import AlteraQuartusPlatform
 
 _io = [
        ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
@@ -92,7 +93,7 @@ _io = [
 class Platform(AlteraQuartusPlatform):
        def __init__(self):
                AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
-                       lambda p: CRG_SE(p, "clk50", None))
+                       lambda p: SimpleCRG(p, "clk50", None))
 
        def do_finalize(self, fragment):
                try:

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 680de17b7520f6135781fea0257d51654ec2e9fe..fe6f91f1a8a109f5337e02e6839ca3deb4662f7a 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -1,5 +1,6 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE, CRG_DS
+from mibuild.crg import SimpleCRG
+from mibuild.xilinx_common import CRG_DS
 from mibuild.xilinx_ise import XilinxISEPlatform
 from mibuild.xilinx_vivado import XilinxVivadoPlatform
 
@@ -90,7 +91,12 @@ def Platform(*args, toolchain="ise", **kwargs):
                raise ValueError
 
        class RealPlatform(xilinx_platform):
-               def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset", 6.4)):
+               def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
                        xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
 
+               def do_finalize(self, fragment):
+                       try:
+                               self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
+                       except ConstraintError:
+                               pass
        return RealPlatform(*args, **kwargs)

diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index 660256cdbfdf1f22c55a15e44aa26dafd2fa0193..e259e4eb3c8d88410092be6df3e752865b25ef49 100644 (file)
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 _io = [
@@ -109,7 +109,7 @@ promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
 """
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
-                               lambda p: CRG_SE(p, "clk_y3", "user_btn"))
+                               lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
                self.add_platform_command("""
 CONFIG VCCAUX = "3.3";
 """)

diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index 4d112d5b0cc64b9925857283671dd96b2a7c8b52..fa4e4beeb01a446038430eb7cbf43ce2745d2302 100644 (file)
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 _io = [
@@ -120,7 +120,7 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
-                       lambda p: CRG_SE(p, "clk50", None))
+                       lambda p: SimpleCRG(p, "clk50", None))
 
        def do_finalize(self, fragment):
                try:

diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index 298474a5c54f37169128a07cae5acb6ec9ca94f3..01f898d2bd413148aef4f08ada4e51a297cdeb99 100644 (file)
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 _io = [
@@ -156,7 +156,7 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
-                       lambda p: CRG_SE(p, "clk50", None))
+                       lambda p: SimpleCRG(p, "clk50", None))
                self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
 
        def do_finalize(self, fragment):

diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py
index 6b649baffd397106892a8442def03a0b69199363..ab263909914cf5c0eedf2b4f8519df7cb45d58ea 100644 (file)
--- a/mibuild/platforms/ml605.py
+++ b/mibuild/platforms/ml605.py
@@ -54,4 +54,10 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
-                       lambda p: CRG_DS(p, "clk200", "user_btn", 5.0))
+                       lambda p: CRG_DS(p, "clk200", "user_btn"))
+
+       def do_finalize(self, fragment):
+               try:
+                       self.add_period_constraint(self.lookup_request("clk200").p, 5)
+               except ConstraintError:
+                       pass

diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py
index 3e21f586af4be14180b93eaa1d8e9325e9f09f41..957d7cfed64e7da1f1b02f5d41944acef63c615d 100644 (file)
--- a/mibuild/platforms/papilio_pro.py
+++ b/mibuild/platforms/papilio_pro.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 _io = [
@@ -51,7 +51,7 @@ _connectors = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
-                       lambda p: CRG_SE(p, "clk32", None), _connectors)
+                       lambda p: SimpleCRG(p, "clk32", None), _connectors)
 
        def do_finalize(self, fragment):
                try:

diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py
index 5af6ea3f3669a2abbc776d9e9439f5e5b8acbb86..e0d05051d84551ab37bc2e13340e93f0dbd4990b 100644 (file)
--- a/mibuild/platforms/rhino.py
+++ b/mibuild/platforms/rhino.py
@@ -136,4 +136,10 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
-                       lambda p: CRG_DS(p, "clk100", "gpio", 10.0))
+                       lambda p: CRG_DS(p, "clk100", "gpio"))
+
+       def do_finalize(self, fragment):
+               try:
+                       self.add_period_constraint(self.lookup_request("clk100").p, 10)
+               except ConstraintError:
+                       pass

diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py
index eb89066e52ca987b22abf1e48fe077bc1358e2ce..33c9fc16d0f6791879a5b6f9dce0125f27c1e5f0 100644 (file)
--- a/mibuild/platforms/zedboard.py
+++ b/mibuild/platforms/zedboard.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 # Bank 34 and 35 voltage depend on J18 jumper setting
@@ -140,7 +140,7 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
-                       lambda p: CRG_SE(p, "clk100", None))
+                       lambda p: SimpleCRG(p, "clk100", None))
 
        def do_finalize(self, fragment):
                try:

diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py
index 27de93621f2f0e1beb6b07110e25a0e155d6bbd2..ece202f67db49cfcc4d6d8e6442aab558c0672ee 100644 (file)
--- a/mibuild/platforms/ztex_115d.py
+++ b/mibuild/platforms/ztex_115d.py
@@ -1,5 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_SE
+from mibuild.crg import SimpleCRG
 from mibuild.xilinx_ise import XilinxISEPlatform
 
 _io = [
@@ -84,7 +84,7 @@ _io = [
 class Platform(XilinxISEPlatform):
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
-                               lambda p: CRG_SE(p, "clk_if", "rst"))
+                               lambda p: SimpleCRG(p, "clk_if", "rst"))
                self.add_platform_command("""
 CONFIG VCCAUX = "2.5";
 """)

diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx_common.py
index aaec951fa9adbc7f5753fbb0524897c8898f5f0e..b9452b72d8d6e77acebe0191fea7c6356074c1a4 100644 (file)
--- a/mibuild/xilinx_common.py
+++ b/mibuild/xilinx_common.py
@@ -1,17 +1,10 @@
 from migen.fhdl.std import *
-from mibuild.crg import SimpleCRG
-
-class CRG_SE(SimpleCRG):
-       def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
-               SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-               platform.add_period_constraint(platform, self._clk, period)
 
 class CRG_DS(Module):
-       def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
+       def __init__(self, platform, clk_name, rst_name, rst_invert=False):
                reset_less = rst_name is None
                self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
                self._clk = platform.request(clk_name)
-               platform.add_period_constraint(platform, self._clk.p, period)
                self.specials += Instance("IBUFGDS",
                        Instance.Input("I", self._clk.p),
                        Instance.Input("IB", self._clk.n),

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 5733a877a96e4dfe417818713b09b0081a884377..56bd414ae821ad9a5cca5ead731104719e742ab7 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -9,8 +9,6 @@ from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
 from mibuild import tools
 
-from mibuild.xilinx_common import CRG_SE, CRG_DS
-
 def _format_constraint(c):
        if isinstance(c, Pins):
                return "LOC=" + c.identifiers[0]
@@ -221,6 +219,5 @@ class XilinxISEPlatform(GenericPlatform):
                os.chdir("..")
 
        def add_period_constraint(self, clk, period):
-               if period is not None:
-                       self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
+               self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
 TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)

diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index 40c0a27d83213b67a2cdb5a19faea6f39f10e691..e7421741da3cac57507954ad9487d5fe0ff9298d 100644 (file)
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
@@ -9,8 +9,6 @@ from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
 from mibuild import tools
 
-from mibuild.xilinx_common import CRG_SE, CRG_DS
-
 def _format_constraint(c):
        if isinstance(c, Pins):
                return "set_property LOC " + c.identifiers[0]
@@ -101,6 +99,5 @@ class XilinxVivadoPlatform(GenericPlatform):
                os.chdir("..")
 
        def add_period_constraint(self, clk, period):
-               if period is not None:
-                       self.add_platform_command("""create_clock -name {clk} -period """ +\
-                               str(period) + """ [get_ports {clk}]""", clk=clk)
+               self.add_platform_command("""create_clock -name {clk} -period """ +\
+                       str(period) + """ [get_ports {clk}]""", clk=clk)