m1crg: fix signal names

diff --git a/load.jtag b/load.jtag
index 8fbe5621d1f894b696530be5eea72ca110bb436e..0379fef0a8c288db2de703c52051dfd5ebf7c19a 100644 (file)
--- a/load.jtag
+++ b/load.jtag
@@ -2,4 +2,4 @@ cable milkymist
 detect
 instruction CFG_OUT  000100 BYPASS
 instruction CFG_IN   000101 BYPASS
-pld load build/soc.bit
+pld load build/top.bit

diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
index f32f3efd28732a876a70b6a72a12c5ff96205b79..8ec923ead25b7b659e4726e5cb39c6b7378302af 100644 (file)
--- a/verilog/m1crg/m1crg.v
+++ b/verilog/m1crg/m1crg.v
@@ -204,7 +204,7 @@ ODDR2 #(
        .INIT(1'b0),
        .SRTYPE("SYNC")
 ) sd_clk_forward_p (
-       .Q(sd_clk_out_p),
+       .Q(ddr_clk_pad_p),
        .C0(clk2x_270),
        .C1(~clk2x_270),
        .CE(1'b1),
@@ -218,7 +218,7 @@ ODDR2 #(
        .INIT(1'b0),
        .SRTYPE("SYNC")
 ) sd_clk_forward_n (
-       .Q(sd_clk_out_n),
+       .Q(ddr_clk_pad_n),
        .C0(clk2x_270),
        .C1(~clk2x_270),
        .CE(1'b1),
@@ -233,7 +233,7 @@ ODDR2 #(
  */
 
 always @(posedge pllout4)
-       eth_clk_pad <= ~eth_clk_pad;
+       eth_phy_clk_pad <= ~eth_phy_clk_pad;
 
 /* Let the synthesizer insert the appropriate buffers */
 assign eth_rx_clk = eth_rx_clk_pad;