{
const char * error;
unsigned long instruction;
- int size;
- int size_req;
- int cond;
+ unsigned int size;
+ unsigned int size_req;
+ unsigned int cond;
/* "uncond_value" is set to the value in place of the conditional field in
- unconditional versions of the instruction, or -1 if nothing is
+ unconditional versions of the instruction, or -1u if nothing is
appropriate. */
- int uncond_value;
+ unsigned int uncond_value;
struct neon_type vectype;
/* This does not indicate an actual NEON instruction, only that
the mnemonic accepts neon-style type suffixes. */
do
{
- int setmask = 1, addregs = 1;
+ unsigned int setmask = 1, addregs = 1;
const char vpr_str[] = "vpr";
- int vpr_str_len = strlen (vpr_str);
+ size_t vpr_str_len = strlen (vpr_str);
new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
inst.operands[i].imm = 0;
for (j = 0; j < parts; j++, idx++)
- inst.operands[i].imm |= generic_bignum[idx]
- << (LITTLENUM_NUMBER_OF_BITS * j);
+ inst.operands[i].imm |= ((unsigned) generic_bignum[idx]
+ << (LITTLENUM_NUMBER_OF_BITS * j));
inst.operands[i].reg = 0;
for (j = 0; j < parts; j++, idx++)
- inst.operands[i].reg |= generic_bignum[idx]
- << (LITTLENUM_NUMBER_OF_BITS * j);
+ inst.operands[i].reg |= ((unsigned) generic_bignum[idx]
+ << (LITTLENUM_NUMBER_OF_BITS * j));
inst.operands[i].regisimm = 1;
}
else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
for (i = 1; i <= 24; i++)
{
a = val >> i;
- if ((val & ~(0xff << i)) == 0)
+ if ((val & ~(0xffU << i)) == 0)
return ((val >> i) & 0x7f) | ((32 - i) << 7);
}
static int
double_to_single (bfd_int64_t v)
{
- int sign = (int) ((v >> 63) & 1l);
- int exp = (int) ((v >> 52) & 0x7FF);
- bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
+ unsigned int sign = (v >> 63) & 1;
+ int exp = (v >> 52) & 0x7FF;
+ bfd_int64_t mantissa = (v & (bfd_int64_t) 0xFFFFFFFFFFFFFULL);
if (exp == 0x7FF)
exp = 0xFF;
l = generic_bignum;
#if defined BFD_HOST_64_BIT
- v =
- ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
- << LITTLENUM_NUMBER_OF_BITS)
- | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
+ v = ((((bfd_uint64_t) l[3] & LITTLENUM_MASK)
<< LITTLENUM_NUMBER_OF_BITS)
- | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
- << LITTLENUM_NUMBER_OF_BITS)
- | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
+ | (((bfd_int64_t) l[2] & LITTLENUM_MASK)
+ << LITTLENUM_NUMBER_OF_BITS)
+ | (((bfd_uint64_t) l[1] & LITTLENUM_MASK)
+ << LITTLENUM_NUMBER_OF_BITS)
+ | (l[0] & LITTLENUM_MASK));
#else
- v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
- | (l[0] & LITTLENUM_MASK);
+ v = ((((valueT) l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
+ | (l[0] & LITTLENUM_MASK));
#endif
}
else
first_error (_(BAD_COND));
return FAIL;
}
- if (inst.uncond_value != -1)
+ if (inst.uncond_value != -1u)
inst.instruction |= inst.uncond_value << 28;
}
case MANUAL_PRED_BLOCK:
{
- int cond, is_last;
+ unsigned int cond;
+ int is_last;
if (now_pred.type == SCALAR_PRED)
{
/* Check conditional suffixes. */
/* The value which unconditional instructions should have in place of the
condition field. */
- inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
+ inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1u;
if (thumb_mode)
{
/* Like negate_data_op, but for Thumb-2. */
static unsigned int
-thumb32_negate_data_op (offsetT *instruction, unsigned int value)
+thumb32_negate_data_op (valueT *instruction, unsigned int value)
{
- int op, new_inst;
- int rd;
+ unsigned int op, new_inst;
+ unsigned int rd;
unsigned int negated, inverted;
negated = encode_thumb32_immediate (-value);
valueT * valP,
segT seg)
{
- offsetT value = * valP;
- offsetT newval;
+ valueT value = * valP;
+ valueT newval;
unsigned int newimm;
unsigned long temp;
int sign;
temp = md_chars_to_number (buf, INSN_SIZE);
/* If the offset is negative, we should use encoding A2 for ADR. */
- if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
+ if ((temp & 0xfff0000) == 0x28f0000 && (offsetT) value < 0)
newimm = negate_data_op (&temp, value);
else
{
&& ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
&& !((temp >> SBIT_SHIFT) & 0x1)
- && value >= 0 && value <= 0xffff)
+ && value <= 0xffff)
{
/* Clear bits[23:20] to change encoding from A1 to A2. */
temp &= 0xff0fffff;
/* Fall through. */
case BFD_RELOC_ARM_LITERAL:
- sign = value > 0;
+ sign = (offsetT) value > 0;
- if (value < 0)
+ if ((offsetT) value < 0)
value = - value;
if (validate_offset_imm (value, 0) == FAIL)
case BFD_RELOC_ARM_OFFSET_IMM8:
case BFD_RELOC_ARM_HWLITERAL:
- sign = value > 0;
+ sign = (offsetT) value > 0;
- if (value < 0)
+ if ((offsetT) value < 0)
value = - value;
if (validate_offset_imm (value, 1) == FAIL)
break;
case BFD_RELOC_ARM_T32_OFFSET_U8:
- if (value < 0 || value > 1020 || value % 4 != 0)
+ if (value > 1020 || value % 4 != 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("bad immediate value for offset (%ld)"), (long) value);
value /= 4;
if ((newval & 0xf0000000) == 0xe0000000)
{
/* Doubleword load/store: 8-bit offset, scaled by 4. */
- if (value >= 0)
+ if ((offsetT) value >= 0)
newval |= (1 << 23);
else
value = -value;
else if ((newval & 0x000f0000) == 0x000f0000)
{
/* PC-relative, 12-bit offset. */
- if (value >= 0)
+ if ((offsetT) value >= 0)
newval |= (1 << 23);
else
value = -value;
else if ((newval & 0x00000100) == 0x00000100)
{
/* Writeback: 8-bit, +/- offset. */
- if (value >= 0)
+ if ((offsetT) value >= 0)
newval |= (1 << 9);
else
value = -value;
else if ((newval & 0x00000f00) == 0x00000e00)
{
/* T-instruction: positive 8-bit offset. */
- if (value < 0 || value > 0xff)
+ if (value > 0xff)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
_("offset out of range"));
else
{
/* Positive 12-bit or negative 8-bit offset. */
- int limit;
- if (value >= 0)
+ unsigned int limit;
+ if ((offsetT) value >= 0)
{
newval |= (1 << 23);
limit = 0xfff;
case BFD_RELOC_ARM_SHIFT_IMM:
newval = md_chars_to_number (buf, INSN_SIZE);
- if (((unsigned long) value) > 32
+ if (value > 32
|| (value == 32
&& (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
{
if ((newval & 0x00100000) == 0)
{
/* 12 bit immediate for addw/subw. */
- if (value < 0)
+ if ((offsetT) value < 0)
{
value = -value;
newval ^= 0x00a00000;
&& (((newval >> 16) & 0xf) == 0xf)
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
&& !((newval >> T2_SBIT_SHIFT) & 0x1)
- && value >= 0 && value <= 0xffff)
+ && value <= 0xffff)
{
/* Toggle bit[25] to change encoding from T2 to T3. */
newval ^= 1 << 25;
break;
case BFD_RELOC_ARM_SMC:
- if (((unsigned long) value) > 0xf)
+ if (value > 0xf)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid smc expression"));
break;
case BFD_RELOC_ARM_HVC:
- if (((unsigned long) value) > 0xffff)
+ if (value > 0xffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid hvc expression"));
newval = md_chars_to_number (buf, INSN_SIZE);
case BFD_RELOC_ARM_SWI:
if (fixP->tc_fix_data != 0)
{
- if (((unsigned long) value) > 0xff)
+ if (value > 0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid swi expression"));
newval = md_chars_to_number (buf, THUMB_SIZE);
}
else
{
- if (((unsigned long) value) > 0x00ffffff)
+ if (value > 0x00ffffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid swi expression"));
newval = md_chars_to_number (buf, INSN_SIZE);
break;
case BFD_RELOC_ARM_MULTI:
- if (((unsigned long) value) > 0xffff)
+ if (value > 0xffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid expression in load/store multiple"));
newval = value | md_chars_to_number (buf, INSN_SIZE);
if (value & temp)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("misaligned branch destination"));
- if ((value & (offsetT)0xfe000000) != (offsetT)0
- && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
+ if ((value & 0xfe000000) != 0
+ && (value & 0xfe000000) != 0xfe000000)
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
if (fixP->fx_done || !seg->use_rela_p)
FIXME: It may be better to remove the instruction completely and
perform relaxation. */
- if (value == -2)
+ if ((offsetT) value == -2)
{
newval = md_chars_to_number (buf, THUMB_SIZE);
newval = 0xbf00; /* NOP encoding T1 */
if ((newval & 0x0f200f00) == 0x0d000900)
{
/* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
- has permitted values that are multiples of 2, in the range 0
+ has permitted values that are multiples of 2, in the range -510
to 510. */
- if (value < -510 || value > 510 || (value & 1))
+ if (value + 510 > 510 + 510 || (value & 1))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
}
else if ((newval & 0xfe001f80) == 0xec000f80)
{
- if (value < -511 || value > 512 || (value & 3))
+ if (value + 511 > 512 + 511 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
}
- else if (value < -1023 || value > 1023 || (value & 3))
+ else if (value + 1023 > 1023 + 1023 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
cp_off_common:
- sign = value > 0;
- if (value < 0)
+ sign = (offsetT) value > 0;
+ if ((offsetT) value < 0)
value = -value;
if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
|| fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
case BFD_RELOC_ARM_CP_OFF_IMM_S2:
case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
- if (value < -255 || value > 255)
+ if (value + 255 > 255 + 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
value *= 4;
_("invalid Hi register with immediate"));
/* If value is negative, choose the opposite instruction. */
- if (value < 0)
+ if ((offsetT) value < 0)
{
value = -value;
subtract = !subtract;
- if (value < 0)
+ if ((offsetT) value < 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("immediate value out of range"));
}
case BFD_RELOC_ARM_THUMB_IMM:
newval = md_chars_to_number (buf, THUMB_SIZE);
- if (value < 0 || value > 255)
+ if (value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid immediate: %ld is out of range"),
(long) value);
/* 5bit shift value (0..32). LSL cannot take 32. */
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
temp = newval & 0xf800;
- if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
+ if (value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("invalid shift value: %ld"), (long) value);
/* Shifts of zero must be encoded as LSL. */
/* REL format relocations are limited to a 16-bit addend. */
if (!fixP->fx_done)
{
- if (value < -0x8000 || value > 0x7fff)
+ if (value + 0x8000 > 0x7fff + 0x8000)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("offset out of range"));
}
bfd_vma encoded_addend = value;
/* Check that addend can be encoded in instruction. */
- if (!seg->use_rela_p && (value < 0 || value > 255))
+ if (!seg->use_rela_p && value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("the offset 0x%08lX is not representable"),
(unsigned long) encoded_addend);
{
bfd_vma insn;
bfd_vma encoded_addend;
- bfd_vma addend_abs = llabs (value);
+ bfd_vma addend_abs = llabs ((offsetT) value);
/* Check that the absolute value of the addend can be
expressed as an 8-bit constant plus a rotation. */
/* If the addend is positive, use an ADD instruction.
Otherwise use a SUB. Take care not to destroy the S bit. */
insn &= 0xff1fffff;
- if (value < 0)
+ if ((offsetT) value < 0)
insn |= 1 << 22;
else
insn |= 1 << 23;
if (!seg->use_rela_p)
{
bfd_vma insn;
- bfd_vma addend_abs = llabs (value);
+ bfd_vma addend_abs = llabs ((offsetT) value);
/* Check that the absolute value of the addend can be
encoded in 12 bits. */
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
- if (value < 0)
+ if ((offsetT) value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
if (!seg->use_rela_p)
{
bfd_vma insn;
- bfd_vma addend_abs = llabs (value);
+ bfd_vma addend_abs = llabs ((offsetT) value);
/* Check that the absolute value of the addend can be
encoded in 8 bits. */
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
- if (value < 0)
+ if ((offsetT) value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
if (!seg->use_rela_p)
{
bfd_vma insn;
- bfd_vma addend_abs = llabs (value);
+ bfd_vma addend_abs = llabs ((offsetT) value);
/* Check that the absolute value of the addend is a multiple of
four and, when divided by four, fits in 8 bits. */
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
- if (value < 0)
+ if ((offsetT) value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
{
fixP->fx_done = 0;
}
- if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
+ if ((value & ~0x7f) && ((value & ~0x3f) != (valueT) ~0x3f))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("branch out of range"));
projects / binutils-gdb.git / commitdiff