Change MemReqPtr parameters to references.

This avoids incrementing and decrementing the MemReq
reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d934299b8f80e3d8781f48ad936a4a4128de6773..0f9ad2cfc0bef76824c9c64b5290925e9ca503d9 100644 (file)
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTlb::checkCacheability(MemReqPtr req)
+AlphaTlb::checkCacheability(MemReqPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
 
 
 Fault
-AlphaItb::translate(MemReqPtr req) const
+AlphaItb::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
 
@@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 }
 
 Fault
-AlphaDtb::translate(MemReqPtr req, bool write) const
+AlphaDtb::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
     Addr pc = regs->pc;

diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index bfcd313e20708e3d8bd44f7f298e7b2da04c7fe6..482a13eee82dc88f285f4fe9903a2a2f6ab3829e 100644 (file)
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -70,7 +70,7 @@ class AlphaTlb : public SimObject
         return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
     }
 
-    static void checkCacheability(MemReqPtr req);
+    static void checkCacheability(MemReqPtr &req);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
@@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb
     AlphaItb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req) const;
+    Fault translate(MemReqPtr &req) const;
 };
 
 class AlphaDtb : public AlphaTlb
@@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb
     AlphaDtb(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr req, bool write) const;
+    Fault translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index f3c4b80152454128bea1d70f7889ca57c08600a8..b49db97200c49944865495be02bf055e74c3face 100644 (file)
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -189,17 +189,17 @@ class ExecContext
     int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
     int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
 
-    Fault translateInstReq(MemReqPtr req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
@@ -214,7 +214,7 @@ class ExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault dummyTranslation(MemReqPtr req)
+    Fault dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -225,15 +225,15 @@ class ExecContext
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
         return No_Fault;
     }
-    Fault translateInstReq(MemReqPtr req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataReadReq(MemReqPtr req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataWriteReq(MemReqPtr req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -241,7 +241,7 @@ class ExecContext
 #endif
 
     template <class T>
-    Fault read(MemReqPtr req, T& data)
+    Fault read(MemReqPtr &req, T& data)
     {
 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
         if (req->flags & LOCKED) {
@@ -254,7 +254,7 @@ class ExecContext
     }
 
     template <class T>
-    Fault write(MemReqPtr req, T& data)
+    Fault write(MemReqPtr &req, T& data)
     {
 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 

diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index db24bb507011bbc567dae9246a699e9f214a7a23..4ec5eed598851bf0ce8d022b134b7a5691173bce 100644 (file)
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
 }
 
 void
-MemTest::completeRequest(MemReqPtr req, uint8_t *data)
+MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
 {
     switch (req->cmd) {
       case Read:

diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 3e7dff9682aeb04462d40ebfdaf3d63ea4db62e1..09f22a17713ef1033faf4fcb47cab127648f2f70 100644 (file)
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -108,7 +108,7 @@ class MemTest : public BaseCPU
     Statistics::Scalar<> numCopies;
 
     // called by MemCompleteEvent::process()
-    void completeRequest(MemReqPtr req, uint8_t *data);
+    void completeRequest(MemReqPtr &req, uint8_t *data);
 
     friend class MemCompleteEvent;
 };
@@ -122,7 +122,7 @@ class MemCompleteEvent : public Event
 
   public:
 
-    MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
+    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
         : Event(&mainEventQueue),
           req(_req), data(_data), tester(_tester)
     {

diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 8e59db93267a9b7b24faba360676d1f0912c58ee..e708be5147b74bb69861d4e73ae4b39532eeb4f2 100644 (file)
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -73,7 +73,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
 }
 
 Fault
-AlphaConsole::read(MemReqPtr req, uint8_t *data)
+AlphaConsole::read(MemReqPtr &req, uint8_t *data)
 {
     memset(data, 0, req->size);
     uint64_t val;
@@ -109,7 +109,7 @@ AlphaConsole::read(MemReqPtr req, uint8_t *data)
 }
 
 Fault
-AlphaConsole::write(MemReqPtr req, const uint8_t *data)
+AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
 {
     uint64_t val;
 

diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 9e774773ee048bfb4059178b42e97b47b8c9c3db..c39b8e8d4b0a94ef1e7a326a073f01bf4d963b91 100644 (file)
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -94,8 +94,8 @@ class AlphaConsole : public MmapDevice
     /**
      * memory mapped reads and writes
      */
-    virtual Fault read(MemReqPtr req, uint8_t *data);
-    virtual Fault write(MemReqPtr req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * standard serialization routines for checkpointing