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Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines
authorClaire Xen <claire@symbioticeda.com>
Tue, 1 Dec 2020 11:31:34 +0000 (12:31 +0100)
committerGitHub <noreply@github.com>
Tue, 1 Dec 2020 11:31:34 +0000 (12:31 +0100)
Fix SYNTHESIS always being defined in Verilog frontend


Trivial merge