Move ABC FF stuff to abc_ff.v; add support for other FD* types

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index d81f828e93ebccf3b031c332f0ef7a135bbbf4e5..f823bd731ec855952f54ae24184a70808232c1df 100644 (file)
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -20,14 +20,124 @@
 
 // ============================================================================
 
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  generate
+    if (IS_PRE_INVERTED)
+      \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+    else
+      \$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
+  endgenerate
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+endmodule
+
+`ifndef _ABC
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
+(* abc_box_id = 1000 *)
+module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q);
+//  assign Q = S ? B : A;
+endmodule
+
+(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
+
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
+module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
+module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+`endif

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 1e1afbc1dc927b42cab337608c1094067adb8ce6..ed283deace938dd9369ff869f3debfe51fc07868 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -57,22 +57,37 @@ RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 
+# Inputs: A B S
+# Outputs: Y
+$__ABC_FD_ASYNC_MUX_ 1000 0 3 1
+0 0 764
+
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 8 1 5 1
+FDRE 1001 1 5 1
 - 109 -46 358 0
 
-# Inputs: C CE D S \$pastQ
+# Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDSE 9 0 5 1
+FDRE_1 1002 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 10 0 5 1
+FDCE 1003 1 5 1
+- 109 - -46 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE_1004 11 1 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 11 0 5 1
+FDPE 1005 1 5 1
+- 109 -46 - 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
 - 109 -46 - 0

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 5ad73aa636b63cc4d6924ee8f28d7bfa2231d7fb..b12b0ed7d9f21c43ca29b9e904a6345a3ee6852d 100644 (file)
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -23,26 +23,9 @@
 `ifndef _NO_FFS
 
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_   (input D, C, output Q);
-`ifndef _ABC
-       FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
-`else
-       wire \$nextQ ;
-       \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0));
-       \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-`endif
-endmodule
-
+module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q);
-`ifndef _ABC
-       FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
-`else
-       wire \$nextQ ;
-       \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0));
-       \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-`endif
-endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 45be9a318a3b8edd5dd42f04ec1f9d00775ca0c8..d5ae124e05b4bc4338daf20295d0ae89163b796d 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -362,7 +362,7 @@ struct SynthXilinxPass : public ScriptPass
                        if (widemux > 0)
                                techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
                        if (abc9)
-                               techmap_args += " -map +/xilinx/ff_map.v";
+                               techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
                        run("techmap " + techmap_args);
                        run("clean");
                }