when you add caches, dma commands within the state machine are delayed and cause...

dev/ns_gige.cc:
    rearrange code so nothing gets skipped when "doing dma."

--HG--
extra : convert_revision : cca66885f45e7df1831e2d8ccaddf5ece7600b13

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index f88fc507f05ff9f80bf87328f05fb96c440766b6..68a50bcce88283cfd9b57f22f7d401a6247566bc 100644 (file)
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -1889,11 +1889,7 @@ NSGigE::txKick()
                 descDmaWrites++;
                 descDmaWrBytes += txDmaLen;
 
-                if (doTxDmaWrite())
-                    goto exit;
-
                 transmit();
-
                 txPacket = 0;
 
                 if (txHalt) {
@@ -1902,6 +1898,9 @@ NSGigE::txKick()
                     txHalt = false;
                 } else
                     txState = txAdvance;
+
+                if (doTxDmaWrite())
+                    goto exit;
             }
         } else {
             DPRINTF(EthernetSM, "this descriptor isn't done yet\n");