Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473a8c145d10af4c3e24b1775206e50949..951d9c66f24c9fb573d480542cc5cc4df45a5a0e 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
     global state.. its a mess) */
 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+       if (!strcmp(yytext, "default"))
+               return TOK_DEFAULT;
        frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
        return TOK_SVA_LABEL;
 }