cpu->activateThread(tid);
break;
- //@TODO: Consider Implementing "Suspend Thread" as Separate from Deallocate
+ //@TODO: Consider Implementing "Suspend Thread" as Separate from
+ //Deallocate
case SuspendThread: // Suspend & Deallocate are same for now.
//cpu->suspendThread(tid);
//break;
default:
fatal("Unrecognized Event Type %d", cpuEventType);
+
}
-
+
cpu->cpuEventRemoveList.push(this);
}
+
+
const char *
InOrderCPU::CPUEvent::description()
{
system(params->system),
physmem(system->physmem),
#endif // FULL_SYSTEM
+#ifdef DEBUG
+ cpuEventNum(0),
+ resReqCount(0),
+#endif // DEBUG
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
// Define dummy instructions and resource requests to be used.
DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
- dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
+ dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
// Reset CPU to reset state.
#if FULL_SYSTEM
/* Register the Resource Pool's stats here.*/
resPool->regStats();
+#ifdef DEBUG
+ maxResReqCount
+ .name(name() + ".maxResReqCount")
+ .desc("Maximum number of live resource requests in CPU")
+ .prereq(maxResReqCount);
+#endif
+
/* Register any of the InOrderCPU's stats here.*/
timesIdled
.name(name() + ".timesIdled")
smtCycles
.name(name() + ".smtCycles")
- .desc("Total number of cycles that the CPU was simultaneous multithreading.(SMT)");
+ .desc("Total number of cycles that the CPU was in SMT-mode");
committedInsts
.init(numThreads)
//Tick next_tick = curTick + cycles(1);
//tickEvent.schedule(next_tick);
mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
- DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", nextCycle(curTick + 1));
+ DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
+ nextCycle(curTick + 1));
}
}
InOrderCPU::addToCurrentThreads(ThreadID tid)
{
if (!isThreadInCPU(tid)) {
- DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
- tid);
+ DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU."
+ "\n", tid);
currentThreads.push_back(tid);
}
}
tid = TheISA::getTargetThread(tcBase(tid));
}
- if (reg_idx < FP_Base_DepTag) { // Integer Register File
+ if (reg_idx < FP_Base_DepTag) {
+ // Integer Register File
return readIntReg(reg_idx, tid);
- } else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
+ } else if (reg_idx < Ctrl_Base_DepTag) {
+ // Float Register File
reg_idx -= FP_Base_DepTag;
return readFloatRegBits(reg_idx, tid);
} else {
void
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
{
- // Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
- // when restoring a thread to the CPU after a fork or after an exception
- // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if it's a branch or not
+ // Set the CPU's PCs - This contributes to the precise state of the CPU
+ // which can be used when restoring a thread to the CPU after a fork or
+ // after an exception
+ // =================
+ // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if
+ // it's a branch or not
setPC(inst->readPC(), tid);
setNextPC(inst->readNextPC(), tid);
setNextNPC(inst->readNextNPC(), tid);
// Broadcast to other resources an instruction
// has been completed
- resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst, tid);
+ resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
+ tid);
// Finally, remove instruction from CPU
removeInst(inst);
{
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
// you want to run w/out caches?
- CacheUnit *cache_res = dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
+ CacheUnit *cache_res =
+ dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
return cache_res->read(inst, addr, data, flags);
}
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags, uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, *(uint64_t*)&data, addr, flags, res);
}
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags, uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, *(uint32_t*)&data, addr, flags, res);
}
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags, uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, (uint32_t)data, addr, flags, res);
}
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
+ mainEventQueue.reschedule(&tickEvent,
+ nextCycle(curTick + ticks(delay)));
else if (!tickEvent.scheduled())
- mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
+ mainEventQueue.schedule(&tickEvent,
+ nextCycle(curTick + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
/** Interface between the CPU and CPU resources. */
ResourcePool *resPool;
- /** Instruction used to signify that there is no *real* instruction in buffer slot */
+ /** Instruction used to signify that there is no *real* instruction in
+ buffer slot */
DynInstPtr dummyBufferInst;
/** Used by resources to signify a denied access to a resource. */
/** Get & Update Next Event Number */
InstSeqNum getNextEventNum()
{
+#ifdef DEBUG
return cpuEventNum++;
+#else
+ return 0;
+#endif
}
/** Register file accessors */
*/
std::queue<ListIt> removeList;
- /** List of all the resource requests that will be removed at the end of this
- * cycle.
+ /** List of all the resource requests that will be removed at the end
+ * of this cycle.
*/
std::queue<ResourceRequest*> reqRemoveList;
// LL/SC debug functionality
unsigned stCondFails;
- unsigned readStCondFailures() { return stCondFails; }
- unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
+
+ unsigned readStCondFailures()
+ { return stCondFails; }
+
+ unsigned setStCondFailures(unsigned st_fails)
+ { return stCondFails = st_fails; }
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(ThreadID tid = 0)
/** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
+#ifdef DEBUG
/** The global event number counter. */
InstSeqNum cpuEventNum;
+ /** Number of resource requests active in CPU **/
+ unsigned resReqCount;
+
+ Stats::Scalar maxResReqCount;
+#endif
+
/** Counter of how many stages have completed switching out. */
int switchCount;
{
instReqsProcessed
.name(name() + ".instReqsProcessed")
- .desc("Number of Instructions Requests that completed in this resource.");
+ .desc("Number of Instructions Requests that completed in "
+ "this resource.");
}
int
void
Resource::freeSlot(int slot_idx)
{
- DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource [slot:%i].\n",
+ DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource "
+ "[slot:%i].\n",
reqMap[slot_idx]->inst->readTid(),
reqMap[slot_idx]->inst->seqNum,
slot_idx);
while (map_it != map_end) {
if ((*map_it).second) {
- DPRINTF(Resource, "Currently Serving request from: [tid:%i] [sn:%i].\n",
+ DPRINTF(Resource, "Currently Serving request from: "
+ "[tid:%i] [sn:%i].\n",
(*map_it).second->getInst()->readTid(),
(*map_it).second->getInst()->seqNum);
}
inst_req = getRequest(inst, stage_num, id, slot_num, cmd);
if (inst->staticInst) {
- DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource.\n",
+ DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this "
+ "resource.\n",
inst->readTid(), inst->seqNum);
} else {
- DPRINTF(Resource, "[tid:%i]: instruction requesting this resource.\n",
+ DPRINTF(Resource, "[tid:%i]: instruction requesting this "
+ "resource.\n",
inst->readTid());
}
do_request = true;
if (inst->staticInst) {
- DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource again.\n",
+ DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource "
+ "again.\n",
inst->readTid(), inst->seqNum);
} else {
DPRINTF(Resource, "[tid:%i]: requesting this resource again.\n",
int ResourceRequest::resReqID = 0;
-int ResourceRequest::resReqCount = 0;
+int ResourceRequest::maxReqCount = 0;
+
+ResourceRequest::ResourceRequest(Resource *_res, DynInstPtr _inst,
+ int stage_num, int res_idx, int slot_num,
+ unsigned _cmd)
+ : res(_res), inst(_inst), cmd(_cmd), stageNum(stage_num),
+ resIdx(res_idx), slotNum(slot_num), completed(false),
+ squashed(false), processing(false), waiting(false)
+{
+#ifdef DEBUG
+ reqID = resReqID++;
+ res->cpu->resReqCount++;
+ DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID,
+ res->cpu->resReqCount);
+
+ if (res->cpu->resReqCount > 100) {
+ fatal("Too many undeleted resource requests. Memory leak?\n");
+ }
+
+ if (res->cpu->resReqCount > maxReqCount) {
+ maxReqCount = res->cpu->resReqCount;
+ res->cpu->maxResReqCount = maxReqCount;
+ }
+
+#endif
+}
+
+ResourceRequest::~ResourceRequest()
+{
+#ifdef DEBUG
+ res->cpu->resReqCount--;
+ DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID,
+ res->cpu->resReqCount);
+#endif
+}
void
ResourceRequest::done(bool completed)
/** Define this function if resource, has a port to connect to an outside
* simulation object.
*/
- virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
+ virtual Port* getPort(const std::string &if_name, int idx)
+ { return NULL; }
/** Return ID for this resource */
int getId() { return id; }
/** Free a resource slot */
virtual void freeSlot(int slot_idx);
- /** Request usage of a resource for this instruction. If this instruction already
- * has made this request to this resource, and that request is uncompleted
- * this function will just return that request
+ /** Request usage of a resource for this instruction. If this instruction
+ * already has made this request to this resource, and that request is
+ * uncompleted this function will just return that request
*/
virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num,
/** Schedule resource event, regardless of its current state. */
void scheduleEvent(int slot_idx, int delay);
- /** Find instruction in list, Schedule resource event, regardless of its current state. */
+ /** Find instruction in list, Schedule resource event, regardless of its
+ * current state. */
bool scheduleEvent(DynInstPtr inst, int delay);
/** Unschedule resource event, regardless of its current state. */
static int resReqID;
- static int resReqCount;
-
+ static int maxReqCount;
+
public:
ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
- int res_idx, int slot_num, unsigned _cmd)
- : res(_res), inst(_inst), cmd(_cmd), stageNum(stage_num),
- resIdx(res_idx), slotNum(slot_num), completed(false),
- squashed(false), processing(false), waiting(false)
- {
- reqID = resReqID++;
- resReqCount++;
- DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
-
- if (resReqCount > 100) {
- fatal("Too many undeleted resource requests. Memory leak?\n");
- }
- }
-
- virtual ~ResourceRequest()
- {
- resReqCount--;
- DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
- }
-
+ int res_idx, int slot_num, unsigned _cmd);
+
+ virtual ~ResourceRequest();
+
int reqID;
/** Acknowledge that this is a request is done and remove
projects / gem5.git / commitdiff