$readmem[hb] file inclusion is now relative to the Verilog file

Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>

diff --git a/CHANGELOG b/CHANGELOG
index 481ba266ed5126b25098a78eeec3ccdbbee88e40..4abfeec06a11a01059d32e8dd3b8be407c9d180a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -53,12 +53,13 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added support for flip-flops with synchronous reset to synth_xilinx
     - Added support for flip-flops with reset and enable to synth_xilinx
     - Added "check -mapped"
-    - Added checking of SystemVerilog always block types (always_comb,
+    - Added checking of SystemVerilog always block types (always_comb, 
       always_latch and always_ff)
     - Added "xilinx_dffopt" pass
     - Added "scratchpad" pass
     - Added "abc9 -dff"
     - Added "synth_xilinx -dff"
+    - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index b94a8d710fab73bb00bba33d765a911bd335e951..f7364b9a800a78a376251d0937051ddde99af080 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2886,7 +2886,8 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
        int meminit_size=0;
 
        std::ifstream f;
-       f.open(mem_filename.c_str());
+       std::string path = filename.substr(0, filename.find_last_of("\\/")+1);
+       f.open(path + mem_filename.c_str());
        yosys_input_files.insert(mem_filename);
 
        if (f.fail())