radeonsi: ubo indexing support (v2)

This is required as part of ARB_gpu_shader5.

no backend changes are required for this, or if
any are, it's the same ones as for samplers.

v2: use get_indirect_index (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 1f2771abecc180dff80dd6e1f5e4f3ae7425a4f2..e3fa1a1ec1bca1802365348bfd08366d35b83605 100644 (file)
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -99,7 +99,7 @@ GL 4.0, GLSL 4.00:
   GL_ARB_gpu_shader5                                   DONE (i965, nvc0)
   - 'precise' qualifier                                DONE
   - Dynamically uniform sampler array indices          DONE (r600, radeonsi, softpipe)
-  - Dynamically uniform UBO array indices              DONE (r600)
+  - Dynamically uniform UBO array indices              DONE (r600, radeonsi)
   - Implicit signed -> unsigned conversions            DONE
   - Fused multiply-add                                 DONE ()
   - Packing/bitfield/conversion functions              DONE (r600, radeonsi, softpipe)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d4a7d3b3617765bc4d4559999d73c9d2b11886a4..81f7bdb3472c1e09fbc449506968d7da49342319 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1191,7 +1191,7 @@ static LLVMValueRef fetch_constant(
        const struct tgsi_ind_register *ireg = &reg->Indirect;
        unsigned buf, idx;
 
-       LLVMValueRef addr;
+       LLVMValueRef addr, bufp;
        LLVMValueRef result;
 
        if (swizzle == LP_CHAN_ALL) {
@@ -1206,7 +1206,7 @@ static LLVMValueRef fetch_constant(
        buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
        idx = reg->Register.Index * 4 + swizzle;
 
-       if (!reg->Register.Indirect) {
+       if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
                if (type != TGSI_TYPE_DOUBLE)
                        return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
                else {
@@ -1216,13 +1216,22 @@ static LLVMValueRef fetch_constant(
                }
        }
 
+       if (reg->Register.Dimension && reg->Dimension.Indirect) {
+               LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+               LLVMValueRef index;
+               index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
+                                                  reg->Dimension.Index);
+               bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
+       } else
+               bufp = si_shader_ctx->const_resource[buf];
+
        addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
        addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
        addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
        addr = lp_build_add(&bld_base->uint_bld, addr,
                            lp_build_const_int32(base->gallivm, idx * 4));
 
-       result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
+       result = buffer_load_const(base->gallivm->builder, bufp,
                                   addr, bld_base->base.elem_type);
 
        if (type != TGSI_TYPE_DOUBLE)