m68k: Implement CAS and TAS patterns.

        * config/m68k/m68k.md (UNSPECV_CAS_1, UNSPECV_CAS_2): New.
        (UNSPECV_TAS_1, UNSPECV_TAS_2): New.
        (I): New mode iterator.
        (xz): New mode attribute.
        * config/m68k/sync.md: New file.

From-SVN: r181747

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0411978ebafc67945f04c1a9063631012a05b8dd..7b81a0e1d9edce530b241b6d57db0b2509538185 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2011-11-26  Richard Henderson  <rth@redhat.com>
 
+       * config/m68k/m68k.md (UNSPECV_CAS_1, UNSPECV_CAS_2): New.
+       (UNSPECV_TAS_1, UNSPECV_TAS_2): New.
+       (I): New mode iterator.
+       (xz): New mode attribute.
+       * config/m68k/sync.md: New file.
+
        * config/m68k/linux.h (TARGET_INIT_LIBFUNCS): New.
        * config/m68k/m68k.c (m68k_init_sync_libfuncs): New.
 

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 672ef0db6c02882aae8c48758a3582a954521e28..e4b4b59afc29d2fb86603612ccfaae3af8c82d3c 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -124,6 +124,10 @@
 
 (define_constants
   [(UNSPECV_BLOCKAGE   0)
+   (UNSPECV_CAS_1      1)
+   (UNSPECV_CAS_2      2)
+   (UNSPECV_TAS_1      3)
+   (UNSPECV_TAS_2      4)
   ])
 
 ;; Registers by name.
@@ -255,6 +259,10 @@
         (const_int 0)]
        (const_int 1)))
 \f
+;; Mode macros for integer operations.
+(define_mode_iterator I [QI HI SI])
+(define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")])
+
 ;; Mode macros for floating point operations.
 ;; Valid floating point modes
 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
@@ -7806,3 +7814,4 @@
   [(set_attr "type" "ib")])
 
 (include "cf.md")
+(include "sync.md")

diff --git a/gcc/config/m68k/sync.md b/gcc/config/m68k/sync.md
new file mode 100644 (file)
index 0000000..9a5bcda
--- /dev/null
+++ b/gcc/config/m68k/sync.md
@@ -0,0 +1,80 @@
+;; GCC machine description for m68k synchronization instructions.
+;; Copyright (C) 2011
+;; Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+(define_expand "atomic_compare_and_swap<mode>"
+  [(match_operand:QI 0 "register_operand" "")          ;; bool success output
+   (match_operand:I 1 "register_operand" "")           ;; oldval output
+   (match_operand:I 2 "memory_operand" "")             ;; memory
+   (match_operand:I 3 "register_operand" "")           ;; expected input
+   (match_operand:I 4 "register_operand" "")           ;; newval input
+   (match_operand:SI 5 "const_int_operand" "")         ;; is_weak
+   (match_operand:SI 6 "const_int_operand" "")         ;; success model
+   (match_operand:SI 7 "const_int_operand" "")]                ;; failure model
+  "TARGET_68020 || TARGET_68040"
+{
+  emit_insn (gen_atomic_compare_and_swap<mode>_1
+            (operands[0], operands[1], operands[2],
+             operands[3], operands[4]));
+  emit_insn (gen_negqi2 (operands[0], operands[0]));
+  DONE;
+})
+
+(define_insn "atomic_compare_and_swap<mode>_1"
+  [(set (match_operand:I 1 "register_operand" "=d")
+       (unspec_volatile:I
+         [(match_operand:I 2 "memory_operand" "+m")
+          (match_operand:I 3 "register_operand" "0")
+          (match_operand:I 4 "register_operand" "d")]
+         UNSPECV_CAS_1))
+   (set (match_dup 2)
+       (unspec_volatile:I
+         [(match_dup 2) (match_dup 3) (match_dup 4)]
+         UNSPECV_CAS_2))
+   (set (match_operand:QI 0 "register_operand" "=d")
+       (unspec_volatile:QI
+         [(match_dup 2) (match_dup 3) (match_dup 4)]
+         UNSPECV_CAS_2))]
+  "TARGET_68020 || TARGET_68040"
+  ;; Elide the seq if operands[0] is dead.
+  "cas<sz> %1,%4,%2\;seq %0")
+
+(define_expand "sync_test_and_setqi"
+  [(match_operand:QI 0 "register_operand" "")
+   (match_operand:QI 1 "memory_operand" "")
+   (match_operand:QI 2 "general_operand" "")]
+  "!(TARGET_68020 || TARGET_68040)"
+{
+  if (operands[2] != const1_rtx)
+    FAIL;
+  emit_insn (gen_sync_test_and_setqi_1 (operands[0], operands[1]));
+  emit_insn (gen_negqi2 (operands[0], operands[0]));
+  DONE;
+})
+
+(define_insn "sync_test_and_setqi_1"
+  [(set (match_operand:QI 0 "register_operand" "=d")
+       (unspec_volatile:QI
+         [(match_operand:QI 1 "memory_operand" "+m")]
+         UNSPECV_TAS_1))
+   (set (match_dup 1)
+       (unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
+  "!(TARGET_68020 || TARGET_68040)"
+  "tas %1\;sne %0")