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add vector length pseudocode
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 17 Apr 2018 06:20:14 +0000
(07:20 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 17 Apr 2018 06:20:14 +0000
(07:20 +0100)
simple_v_extension.mdwn
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diff --git
a/simple_v_extension.mdwn
b/simple_v_extension.mdwn
index ad2ced559b285622555951a06b1df497a92124b2..98791b0076f54f135eb6cf6636cc9bdc1901698e 100644
(file)
--- a/
simple_v_extension.mdwn
+++ b/
simple_v_extension.mdwn
@@
-1073,6
+1073,7
@@
This is interpreted as follows:
* Given that the context is RV32, ELEN=32.
* With ELEN=32 and bitwidth=16, the number of SIMD elements is 2
* Therefore the actual vector length is up to *six* elements
+* However vsetl sets a length 5 therefore the last "element" is skipped
So when using an operation that uses r2 as a source (or destination)
the operation is carried out as follows: