add extra ops csv

diff --git a/openpower/isatables.mdwn b/openpower/isatables.mdwn
index 56e647800f04857195903efa98b1f991c153bd16..9bb520c06b7bc4f54d6b66bed7d7e442f6dc8171 100644 (file)
--- a/openpower/isatables.mdwn
+++ b/openpower/isatables.mdwn
@@ -2,6 +2,8 @@
 
 TODO
 
+Based on Anton Blanchard's microwatt decode1.vhdl
+
 ## Major opcodes
 
 [[!table format=csv file="openpower/isatables/major.csv"]]

diff --git a/openpower/isatables/extra.csv b/openpower/isatables/extra.csv
new file mode 100644 (file)
index 0000000..a122a5a
--- /dev/null
+++ b/openpower/isatables/extra.csv
@@ -0,0 +1,4 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe
+attn,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn
+nop,ALU,OP_NOP,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop
+sim_cfg,ALU,OP_SIM_CONFIG,NONE,NONE,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg