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diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 665781cd1783c768850d609c496a84f2ef83259e..2c47674f00a5e497434add07d4d604d2b3e5cfa7 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -185,13 +185,15 @@ ultimately rational quirks.
 # Twin Predication
 
 Twin Predication is an entirely new concept not present in any commercial
-Vector ISA of the past forty years.  To explain:
+Vector ISA of the past forty years.  To explain how normal Single-predication
+is applied in a standard Vector ISA:
 
-* Predication on the destination of a LOAD instruction creates something
+* Predication on the **destination** of a LOAD instruction creates something
   called "Vector Compressed Load" (VCOMPRESS).
-* Predication on the *source* of a STORE instruction creates something
+* Predication on the **source** of a STORE instruction creates something
   called "Vector Expanded Store" (VEXPAND).
-* SVP64 allows the two to be put back-to-back.
+* SVP64 allows the two to be put back-to-back: one on source, one on
+  destination.
 
 The above allows a reader familiar with VCOMPRESS and VEXPAND to
 conceptualise what the effect of Twin Predication is, but it actually
@@ -204,11 +206,12 @@ operations.
 No other Vector ISA in the world has this capability.  All true Vector
 ISAs have Predicate Masks: it is an absolutely essential characteristic.
 However none of them have abstracted dual predicates out to the extent
-where they are applicable *in general* to a wide range of arithmetic
+where this VCOMPRESS-VEXPAND effect is applicable *in general* to a
+wide range of arithmetic
 instructions, as well as Load/Store.
 
 It is however important to note that not all instructions can be Twin
-Predicated: some remain only Single Predicated, as is normally found
+Predicated (2P): some remain only Single Predicated (1P), as is normally found
 in other Vector ISAs. Arithmetic operations with
 four registers (3-in, 1-out, VA-Form for example) are Single. The reason
 is that there just wasn't enough space in the 24-bits of the SVP64 Prefix.