cpu: remove initial SERV support (we'll work in a branch to experiment with it)

diff --git a/.gitmodules b/.gitmodules
index 8587dd82d2883b6b016ef026ef4c7b7a0f5a3981..17eaf734d30bb58526a0fc3ce4c43102c1ae8c4f 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -22,6 +22,3 @@
 [submodule "litex/soc/cores/cpu/rocket/verilog"]
        path = litex/soc/cores/cpu/rocket/verilog
        url = https://github.com/enjoy-digital/rocket-litex-verilog
-[submodule "litex/soc/cores/cpu/serv/verilog"]
-       path = litex/soc/cores/cpu/serv/verilog
-       url = https://github.com/olofk/serv

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index b8d6aad2fa654f8fbab12da0cf6e16d4d1be9b14..236dba4b427092e3264b8e9f3e40aa287aa86b21 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -30,7 +30,6 @@ from litex.soc.cores.cpu.picorv32 import PicoRV32
 from litex.soc.cores.cpu.vexriscv import VexRiscv
 from litex.soc.cores.cpu.minerva import Minerva
 from litex.soc.cores.cpu.rocket import RocketRV64
-from litex.soc.cores.cpu.serv import SERV
 
 CPUS = {
     "lm32"       : LM32,
@@ -39,7 +38,6 @@ CPUS = {
     "vexriscv"   : VexRiscv,
     "minerva"    : Minerva,
     "rocket"     : RocketRV64,
-    "serv"       : SERV
 }
 
 # CPU Variants/Extensions Definition ---------------------------------------------------------------

diff --git a/litex/soc/cores/cpu/serv/__init__.py b/litex/soc/cores/cpu/serv/__init__.py
deleted file mode 100644 (file)
index b46284a..0000000
--- a/litex/soc/cores/cpu/serv/__init__.py
+++ /dev/null
@@ -1 +0,0 @@
-from litex.soc.cores.cpu.serv.core import SERV

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
deleted file mode 100644 (file)
index d5b8ce3..0000000
--- a/litex/soc/cores/cpu/serv/core.py
+++ /dev/null
@@ -1,96 +0,0 @@
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
-
-# License: BSD
-
-import os
-
-from migen import *
-
-from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
-
-
-CPU_VARIANTS = ["standard"]
-
-
-class SERV(CPU):
-    name                 = "serv"
-    data_width           = 32
-    endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf")
-    linker_output_format = "elf32-littleriscv"
-
-    @property
-    def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
-
-    @property
-    def gcc_flags(self):
-        flags =  "-march=rv32i "
-        flags += "-mabi=ilp32 "
-        flags += "-D__serv__ "
-        return flags
-
-    @property
-    def linker_output_format(self):
-        return "elf32-littleriscv"
-
-    def __init__(self, platform, variant="standard"):
-        assert variant is "standard", "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.ibus      = wishbone.Interface()
-        self.dbus      = wishbone.Interface()
-        self.interrupt = Signal(32)
-
-        # # #
-
-        self.cpu_params = dict(
-            # clock / reset
-            i_clk   = ClockSignal(),
-            i_i_rst = ResetSignal(),
-
-            # timer irq
-            i_i_timer_irq = 0,
-
-            # ibus
-            o_o_ibus_adr = self.ibus.adr,
-            o_o_ibus_cyc = self.ibus.cyc,
-            i_i_ibus_rdt = self.ibus.dat_r,
-            i_i_ibus_ack = self.ibus.ack,
-
-
-            # dbus
-            o_o_dbus_adr = self.dbus.adr,
-            o_o_dbus_dat = self.dbus.dat_w,
-            o_o_dbus_sel = self.dbus.sel,
-            o_o_dbus_we  = self.dbus.we,
-            o_o_dbus_cyc = self.dbus.cyc,
-            i_i_dbus_rdt = self.dbus.dat_r,
-            i_i_dbus_ack = self.dbus.ack,
-        )
-        self.comb += [
-            self.ibus.stb.eq(self.ibus.cyc),
-            self.dbus.stb.eq(self.dbus.cyc),
-        ]
-
-        # add verilog sources
-        self.add_sources(platform)
-
-    def set_reset_address(self, reset_address):
-        assert not hasattr(self, "reset_address")
-        self.reset_address = reset_address
-        self.cpu_params.update(p_RESET_PC=reset_address)
-
-    @staticmethod
-    def add_sources(platform):
-        vdir = os.path.join(
-            os.path.abspath(os.path.dirname(__file__)),
-            "verilog", "rtl")
-        platform.add_source_dir(vdir)
-        platform.add_verilog_include_path(vdir)
-
-    def do_finalize(self):
-        assert hasattr(self, "reset_address")
-        self.specials += Instance("serv_top", **self.cpu_params)

diff --git a/litex/soc/software/bios/boot-helper-serv.S b/litex/soc/software/bios/boot-helper-serv.S
deleted file mode 100644 (file)
index e8bd5c7..0000000
--- a/litex/soc/software/bios/boot-helper-serv.S
+++ /dev/null
@@ -1,4 +0,0 @@
-       .section .text, "ax", @progbits
-       .global boot_helper
-boot_helper:
-       jr x13

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 897c03d50f23789e2cc73467fddb5840df872cc8..f0c12edfe7188eb643440b961da6fb97cf37b3ce 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -44,8 +44,6 @@ __attribute__((unused)) static void cdelay(int i)
                __asm__ volatile("nop");
 #elif defined (__powerpc__)
                __asm__ volatile("nop");
-#elif defined (__serv__)
-               __asm__ volatile("nop");
 #else
 #error Unsupported architecture
 #endif

diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h
index 0a0766e8360c76e28778f12ca1b3183da3ec7fd7..4bf6786c4569af6209a338a5a3558fd7eda5f423 100644 (file)
--- a/litex/soc/software/include/base/irq.h
+++ b/litex/soc/software/include/base/irq.h
@@ -56,8 +56,6 @@ static inline unsigned int irq_getie(void)
        return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
 #elif defined (__rocket__)
        return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-#elif defined (__serv__)
-       return 0; /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -83,8 +81,6 @@ static inline void irq_setie(unsigned int ie)
        if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
 #elif defined (__rocket__)
        if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-#elif defined (__serv__)
-       /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -112,8 +108,6 @@ static inline unsigned int irq_getmask(void)
        return mask;
 #elif defined (__rocket__)
        return csr_readl(PLIC_ENABLED) >> 1;
-#elif defined (__serv__)
-       return 0; /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -135,8 +129,6 @@ static inline void irq_setmask(unsigned int mask)
        asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
 #elif defined (__rocket__)
        csr_writel(mask << 1, PLIC_ENABLED);
-#elif defined (__serv__)
-       /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -162,8 +154,6 @@ static inline unsigned int irq_pending(void)
        return pending;
 #elif defined (__rocket__)
        return csr_readl(PLIC_PENDING) >> 1;
-#elif defined (__serv__)
-       return 0;/* FIXME */
 #else
 #error Unsupported architecture
 #endif

diff --git a/litex/soc/software/libbase/crt0-serv.S b/litex/soc/software/libbase/crt0-serv.S
deleted file mode 100644 (file)
index 6f6e9e6..0000000
--- a/litex/soc/software/libbase/crt0-serv.S
+++ /dev/null
@@ -1,63 +0,0 @@
-#define MIE_MEIE       0x800
-
-       .global _start
-_start:
-       j reset_vector
-
-reset_vector:
-       la sp, _fstack
-       la t0, trap_vector
-       csrw mtvec, t0
-
-       // initialize .bss
-       la t0, _fbss
-       la t1, _ebss
-1:     beq t0, t1, 2f
-       sw zero, 0(t0)
-       addi t0, t0, 4
-       j 1b
-2:
-       // enable external interrupts
-       li t0, MIE_MEIE
-       csrs mie, t0
-
-       call main
-1:     j 1b
-
-trap_vector:
-       addi sp, sp, -16*4
-       sw ra,  0*4(sp)
-       sw t0,  1*4(sp)
-       sw t1,  2*4(sp)
-       sw t2,  3*4(sp)
-       sw a0,  4*4(sp)
-       sw a1,  5*4(sp)
-       sw a2,  6*4(sp)
-       sw a3,  7*4(sp)
-       sw a4,  8*4(sp)
-       sw a5,  9*4(sp)
-       sw a6, 10*4(sp)
-       sw a7, 11*4(sp)
-       sw t3, 12*4(sp)
-       sw t4, 13*4(sp)
-       sw t5, 14*4(sp)
-       sw t6, 15*4(sp)
-       call isr
-       lw ra,  0*4(sp)
-       lw t0,  1*4(sp)
-       lw t1,  2*4(sp)
-       lw t2,  3*4(sp)
-       lw a0,  4*4(sp)
-       lw a1,  5*4(sp)
-       lw a2,  6*4(sp)
-       lw a3,  7*4(sp)
-       lw a4,  8*4(sp)
-       lw a5,  9*4(sp)
-       lw a6, 10*4(sp)
-       lw a7, 11*4(sp)
-       lw t3, 12*4(sp)
-       lw t4, 13*4(sp)
-       lw t5, 14*4(sp)
-       lw t6, 15*4(sp)
-       addi sp, sp, 16*4
-       mret

diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index 73e657785aa22d1b56f55631d441c87c750394cc..bb15aad06e70e188018dff30a0310a5c49944d6a 100644 (file)
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -56,9 +56,6 @@ void flush_cpu_icache(void)
 #elif defined (__rocket__)
        /* FIXME: do something useful here! */
        asm volatile("nop");
-#elif defined (__serv__)
-       /* no instruction cache */
-       asm volatile("nop");
 #else
 #error Unsupported architecture
 #endif
@@ -104,9 +101,6 @@ void flush_cpu_dcache(void)
 #elif defined (__rocket__)
        /* FIXME: do something useful here! */
        asm volatile("nop");
-#elif defined (__serv__)
-       /* no data cache */
-       asm volatile("nop");
 #else
 #error Unsupported architecture
 #endif