FREE(query);
}
+static void si_inhibit_clockgating(struct si_context *sctx, bool inhibit)
+{
+ if (sctx->chip_class >= GFX10) {
+ radeon_set_uconfig_reg(sctx->gfx_cs, R_037390_RLC_PERFMON_CLK_CNTL,
+ S_037390_PERFMON_CLOCK_STATE(inhibit));
+ } else if (sctx->chip_class >= GFX8) {
+ radeon_set_uconfig_reg(sctx->gfx_cs, R_0372FC_RLC_PERFMON_CLK_CNTL,
+ S_0372FC_PERFMON_CLOCK_STATE(inhibit));
+ }
+}
+
static void si_pc_query_resume(struct si_context *sctx, struct si_query *squery)
/*
struct si_query_hw *hwquery,
if (query->shaders)
si_pc_emit_shaders(sctx, query->shaders);
+ si_inhibit_clockgating(sctx, true);
+
for (struct si_query_group *group = query->groups; group; group = group->next) {
struct si_pc_block *block = group->block;
}
si_pc_emit_instance(sctx, -1, -1);
+
+ si_inhibit_clockgating(sctx, false);
}
static bool si_pc_query_begin(struct si_context *ctx, struct si_query *squery)