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diff --git a/doc/migScope.rst b/doc/migScope.rst
index a8f4d718c8dcec2800370807f66d668f480de97c..bd46e83f7518a34019f88e92103cab93998c749f 100644 (file)
--- a/doc/migScope.rst
+++ b/doc/migScope.rst
@@ -3,7 +3,7 @@ Introduction
 
 MigScope is a small logic analyzer to be embedded in an FPGA.
 
-While free vendor's toolchains are generally used by beginners or for prototyping (situations where having a logic analyser in the design is generally very helpfull) free toolchains are always provided without the proprietary logic analyzer solution...:(
+While free vendor toolchains are generally used by beginners or for prototyping ( situations where having a logic analyser in the design is generally very helpfull) free toolchains are always provided without the proprietary logic analyzer solution. . . :(
 
 Based on Migen, MigScope aims to provide a free and more portable / flexible alternative to vendor's solutions.
 
@@ -17,8 +17,7 @@ Migen makes it possible to apply modern software concepts such as object-oriente
 
 Installing MigScope
 *******************
-Either run the setup.py installation script or simply set PYTHONPATH to the
-root of the source directory.
+Either run the setup.py installation script or simply set PYTHONPATH to the root of the source directory.
 
 Feedback
 ********
@@ -33,17 +32,17 @@ Migscope provides two kinds of cores:
   - MigIo : the virtual Input / Output core
   - MigLa : the virtual Logic Analyser core
 
-A CSR bus controls the MigIo and MigLa cores.The CSR bus is a very simple bus originally used to control peripheral's registers in milkymist Soc.[*]_
+A CSR bus controls the MigIo and MigLa cores. The CSR bus is a very simple bus originally used to control peripheral registers in milkymist Soc.[*]_
 
 .. [*] More information on Milkymist on : http://github.com/milkymist/milkymist-ng
 
-Because it's simplicity, it can be adapted very easily to a wide range of interfaces: Wishbone, Uart, Spi, I2C, Ethernet...
+Because of its simplicity, it can be adapted very easily to a wide range of interfaces: Wishbone, Uart, Spi, I2C, Ethernet...
 
-MigScope uses CSR library from Migen to inter-connect cores. MigScope provides a Spi2Csr Bridge and is tested with an external Spi Interface. Support of others external interface will be added in future versions.
+MigScope uses CSR library from Migen to inter-connect the cores. MigScope provides a Spi2Csr Bridge and is tested with an external Spi Interface. Support for others externals interfaces will be added in future versions.
 
-Because Migen is a Python-based tool, using Python to control MigScope gives us lot's of advantages : Python Class can provides the HDL description **AND** the driver functions!
+Because Migen is a Python-based tool, using Python to control MigScope gives lot's of advantages : Python classes can provide the HDL description **AND** driver functions!
 
-*MigScope Structure Schematic*
+.. image:: Illustrations/migscope_structure.png
 
 MigIo
 #####
@@ -51,14 +50,14 @@ MigIo
 Description
 -----------
 
-The MigIo is simply an internal GPIO equivalent. It provides N (configurable) inputs and/or outputs and can be used for lot's of purposes:
+The MigIo is simply an internal GPIO equivalent. It provides N (configurable) inputs and/or outputs and can be used for lots of purposes:
 
   - stimulation of a core's parameters in a design where external control interface is not yet developped or still under developpement.
-  - update of a Look-Up-Table or a Ram in the design.
-  - read an internal / external bus values
+  - update of a Look-Up-Table or a Ram.
+  - read an internal / external bus.
   - ...
 
-*MigIo Structure Schematic*
+.. image:: Illustrations/migIo.png
 
 
 Instanciation
@@ -76,12 +75,12 @@ MigIo parameters are:
 
 Driver
 ------
-To use drivers functions, an interface must be defined::
+To use drivers functions, an interface is defined::
 
   csr = Uart2Spi(1,115200)
   migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
 
-MigIo drivers functions will now use our csr interface. Note that it is only useful to define the migIo interface in the Python code that will be executed on the Host, the code that will be translated in HDL don't need it.
+MigIo drivers functions will now use our csr interface. Note that it's only useful to define the migIo interface in the Python code that will be executed on the Host, the code that will be translated in HDL don't need it.
 
 Write Method::
 
@@ -109,4 +108,6 @@ The HDL Code is in examples/deX/top.py
 The Host Code is in examples/deX/client/test_MigIo.py
 
 MigLa
-#####
\ No newline at end of file
+#####
+
+[To Be Done]
\ No newline at end of file

diff --git a/migScope/recorder.py b/migScope/recorder.py
index a8570c3b15e6b8d839afb3bcf9f8a4993c2bbca9..0c2aec1a5a19523e2873f92182b2e4d4d6578717 100644 (file)
--- a/migScope/recorder.py
+++ b/migScope/recorder.py
@@ -218,7 +218,6 @@ class Recorder:
                return self.interface.read(self.address + 0x02) == 1
                
        def size(self, dat):
-               self.size = dat
                self.interface.write_n(self.address + 0x03, dat, 16)
                
        def offset(self, dat):