iris: actually pin the buffers

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 24d891f97fdeb0803aa7919995a26f6e6538d84c..d62935a08320c8883a645483f0d2d039aba5d926 100644 (file)
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -285,8 +285,9 @@ struct iris_context {
       unsigned num_samplers[MESA_SHADER_STAGES];
       unsigned num_textures[MESA_SHADER_STAGES];
 
-      /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
+      struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
       bool streamout_active;
+      /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
       uint32_t *streamout;
 
       struct iris_state_ref unbound_tex;

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 089458d2b70bdcd865b50a15acab55f36fef99b2..e4ecba6825491bb40e415ae62dcd76c9fdd184f0 100644 (file)
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1708,6 +1708,11 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
       ice->state.dirty |= IRIS_DIRTY_STREAMOUT;
    }
 
+   for (int i = 0; i < 4; i++) {
+      pipe_so_target_reference(&ice->state.so_target[i],
+                               i < num_targets ? targets[i] : NULL);
+   }
+
    /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
    if (!active)
       return;
@@ -2893,6 +2898,15 @@ iris_upload_render_state(struct iris_context *ice,
    if (dirty & IRIS_DIRTY_SO_BUFFERS) {
       iris_batch_emit(batch, genx->so_buffers,
                       4 * 4 * GENX(3DSTATE_SO_BUFFER_length));
+      for (int i = 0; i < 4; i++) {
+         struct iris_stream_output_target *tgt =
+            (void *) ice->state.so_target[i];
+         if (tgt) {
+            iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
+                               true);
+            iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res), true);
+         }
+      }
    }
 
    if ((dirty & IRIS_DIRTY_SO_DECL_LIST) && ice->state.streamout) {