Support adding Verilog/VHDL files

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index bc03cf32af09792ae239f465c9277cf71ee35edb..b78f2a4cda9cefee5d9f3d71e2c0d89d7c1dfcdc 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -1,9 +1,12 @@
 from copy import copy
+import os
 
 from migen.fhdl.structure import *
 from migen.corelogic.record import Record
 from migen.fhdl import verilog
 
+from mibuild import tools
+
 class ConstraintError(Exception):
        pass
        
@@ -166,6 +169,7 @@ class GenericPlatform:
                self.device = device
                self.constraint_manager = ConstraintManager(io)
                self.default_crg_factory = default_crg_factory
+               self.sources = []
 
        def request(self, *args, **kwargs):
                return self.constraint_manager.request(*args, **kwargs)
@@ -173,6 +177,24 @@ class GenericPlatform:
        def add_platform_command(self, *args, **kwargs):
                return self.constraint_manager.add_platform_command(*args, **kwargs)
 
+       def add_source(self, filename, language=None):
+               if language is None:
+                       language = tools.language_by_filename(filename)
+               if language is None:
+                       language = "verilog" # default to Verilog
+               self.sources.append((filename, language))
+
+       def add_sources(self, path, *filenames, language=None):
+               for f in filenames:
+                       self.add_source(os.path.join(path, f), language)
+
+       def add_source_dir(self, path):
+               for root, dirs, files in os.walk(path):
+                       for filename in files:
+                               language = tools.language_by_filename(filename)
+                               if language is not None:
+                                       self.add_source(os.path.join(root, filename), language)
+
        def get_verilog(self, fragment, clock_domains=None):
                # We may create a temporary clock/reset generator that would request pins.
                # Save the constraint manager state so that such pin requests disappear

diff --git a/mibuild/tools.py b/mibuild/tools.py
index 565312a26938b99765724931fa18a7368b4f41e3..1c2493e4e5744a4a09fcbeba6c8968d6b3d5904c 100644 (file)
--- a/mibuild/tools.py
+++ b/mibuild/tools.py
@@ -6,6 +6,14 @@ def mkdir_noerror(d):
        except OSError:
                pass
 
+def language_by_filename(name):
+       extension = name.rsplit(".")[-1] 
+       if extension in ["v", "vh", "vo"]:
+               return "verilog"
+       if extension in ["vhd", "vhdl", "vho"]:
+               return "vhdl"
+       return None
+
 def write_to_file(filename, contents):
        f = open(filename, "w")
        f.write(contents)

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index ce82b383c456d8505320e66e841a1e15278c6a47..d13945d43bff25edfca588538dfc71319a5b9aff 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -64,8 +64,8 @@ def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path)
        tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
 
        prj_contents = ""
-       for s in sources:
-               prj_contents += s["type"] + " work " + s["path"] + "\n"
+       for filename, language in sources:
+               prj_contents += language + " work " + filename + "\n"
        tools.write_to_file(build_name + ".prj", prj_contents)
 
        xst_contents = """run
@@ -116,7 +116,7 @@ class XilinxISEPlatform(GenericPlatform):
                v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
-               sources = [{"type": "verilog", "path": v_file}]
+               sources = self.sources + [(v_file, "verilog")]
                _build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path)
                
                os.chdir("..")