ac: add radeon_info::use_late_alloc to control LATE_ALLOC globally

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 4f928a8b51feb5fa95c5c2d446c86e63d685a237..e53a1a15afc3ebc264d3cd19f968b86dee26d0d6 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -717,14 +717,18 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
                info->min_sgpr_alloc = 128;
                info->sgpr_alloc_granularity = 128;
+               info->use_late_alloc = true;
        } else if (info->chip_class >= GFX8) {
                info->num_physical_sgprs_per_simd = 800;
                info->min_sgpr_alloc = 16;
                info->sgpr_alloc_granularity = 16;
+               info->use_late_alloc = true;
        } else {
                info->num_physical_sgprs_per_simd = 512;
                info->min_sgpr_alloc = 8;
                info->sgpr_alloc_granularity = 8;
+               /* Potential hang on Kabini: */
+               info->use_late_alloc = info->family != CHIP_KABINI;
        }
 
        info->max_sgpr_alloc = info->family == CHIP_TONGA ||

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 93cf323372c677892d5da64dbf16e34ef2246d30..20a2f79eb63ee5ceb2c126b9fa56d8fa7e456ed5 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -169,6 +169,7 @@ struct radeon_info {
        uint32_t                    min_wave64_vgpr_alloc;
        uint32_t                    max_vgpr_alloc;
        uint32_t                    wave64_vgpr_alloc_granularity;
+       bool                        use_late_alloc; /* VS and GS: late pos/param allocation */
 
        /* Render backends (color + depth blocks). */
        uint32_t                    r300_num_gb_pipes;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 418048f940215d6d715bdf5f9c6dd35eced74351..46d7c71b2de6fee05b5da1a43329a15b4b4de514 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5566,7 +5566,9 @@ static void si_init_config(struct si_context *sctx)
                        /* For Wave32, the hw will launch twice the number of late
                         * alloc waves, so 1 == 2x wave32.
                         */
-                       if (num_cu_per_sh <= 6) {
+                       if (!sscreen->info.use_late_alloc) {
+                               late_alloc_wave64 = 0;
+                       } else if (num_cu_per_sh <= 6) {
                                late_alloc_wave64 = num_cu_per_sh - 2;
                        } else {
                                late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
@@ -5578,8 +5580,8 @@ static void si_init_config(struct si_context *sctx)
                                             sctx->family != CHIP_NAVI14 ? 0xfff3 : 0xffff;
                        }
                } else {
-                       if (sctx->family == CHIP_KABINI) {
-                               late_alloc_wave64 = 0; /* Potential hang on Kabini. */
+                       if (!sscreen->info.use_late_alloc) {
+                               late_alloc_wave64 = 0;
                        } else if (num_cu_per_sh <= 4) {
                                /* Too few available compute units per SH. Disallowing
                                 * VS to run on one CU could hurt us more than late VS

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 448ea8c732bf463618acd9c0b4474334787e06f1..212995637779e7b5491fd2f7f5ae9b5976d32f25 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1227,7 +1227,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
         *
         * Don't use late alloc for NGG on Navi14 due to a hw bug.
         */
-       if (sscreen->info.family == CHIP_NAVI14)
+       if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
                late_alloc_wave64 = 0;
        else if (num_cu_per_sh <= 6)
                late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
@@ -1318,7 +1318,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
        }
 
        unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
-       shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
+       shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
                                          S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
 
        if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
@@ -1528,7 +1528,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
                        S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
                                                    V_02870C_SPI_SHADER_4COMP :
                                                    V_02870C_SPI_SHADER_NONE);
-       shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
+       shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
                                         S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
        shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
 

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index fca5be58751647a18d4aa44a0566fe023a0bae4a..8dde57200bd4ec12e78807d2a4745eb36198a565 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -597,6 +597,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.max_wave64_per_simd = 10;
     ws->info.num_physical_sgprs_per_simd = 512;
     ws->info.num_physical_wave64_vgprs_per_simd = 256;
+    /* Potential hang on Kabini: */
+    ws->info.use_late_alloc = ws->info.family != CHIP_KABINI;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
                    strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;