move standards tagged to bottom of page

diff --git a/resources.mdwn b/resources.mdwn
index e5a46b09f704fe4fea325e8ae0de849a11dc9f9b..4a99fc590d3d260da9755e33bc0054f71e82e25e 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -4,13 +4,6 @@ This page aims to collect all the resources and specifications we need
 in one place for quick access. We will try our best to keep links here
 up-to-date. Feel free to add more links here.
 
-# Libre-RISC-V Standards
-
-This list auto-generated from a page tag "standards":
-
-[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
-
-
 # RISC-V Instruction Set Architecture
 
 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
@@ -160,6 +153,7 @@ the Khronos standards until we actually make an official submission,
 do the paperwork, and pay the relevant fees.
 
 ## Formal Verification
+
 Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify.
 Of course, it is important to do the formal verification as a final step in the development process before
 we produce thousands or millions of silicon.
@@ -177,3 +171,10 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 
 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+# Libre-RISC-V Standards
+
+This list auto-generated from a page tag "standards":
+
+[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
+
+