integration/soc_core: revert integrate_sram_size default value (cause issues when...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 29 Jan 2020 07:31:41 +0000 (08:31 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 29 Jan 2020 07:31:41 +0000 (08:31 +0100)
When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.

litex/soc/integration/soc_core.py

index 6f61a213900a032e6321ba26fc4e6073441012b7..33240ff2b7ff6712fed0f612d7bf1b667d8bb4a0 100644 (file)
@@ -87,7 +87,7 @@ class SoCCore(Module):
                 # ROM parameters
                 integrated_rom_size=0, integrated_rom_init=[],
                 # SRAM parameters
-                integrated_sram_size=0, integrated_sram_init=[],
+                integrated_sram_size=0x1000, integrated_sram_init=[],
                 # MAIN_RAM parameters
                 integrated_main_ram_size=0, integrated_main_ram_init=[],
                 # CSR parameters
@@ -139,10 +139,8 @@ class SoCCore(Module):
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
-        if cpu_type is not None and integrated_sram_size == 0:
-            integrated_sram_size = 0x1000
-        self.integrated_sram_size     = integrated_sram_size
-        self.integrated_main_ram_size = integrated_main_ram_size
+        self.integrated_sram_size       = integrated_sram_size
+        self.integrated_main_ram_size   = integrated_main_ram_size
 
         assert csr_data_width in [8, 16, 32]
         self.csr_data_width    = csr_data_width