#ifndef __ARCH_RISCV_PAGETABLE_H__
#define __ARCH_RISCV_PAGETABLE_H__
+#include "base/bitunion.hh"
#include "base/logging.hh"
#include "base/trie.hh"
#include "base/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/riscv/generated/max_inst_regs.hh"
+#include "base/bitunion.hh"
#include "base/types.hh"
namespace RiscvISA {
#ifndef __DEV_ARM_GLOBAL_TIMER_HH__
#define __DEV_ARM_GLOBAL_TIMER_HH__
+#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "params/A9GlobalTimer.hh"
#ifndef __DEV_PS2_MOUSE_HH__
#define __DEV_PS2_MOUSE_HH__
+#include "base/bitunion.hh"
#include "dev/ps2/device.hh"
struct PS2MouseParams;
#include <deque>
+#include "base/bitunion.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/ps2/device.hh"
#include <type_traits>
#include <vector>
+#include "base/bitfield.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "mem/cache/compressors/base.hh"
#include <string>
#include <unordered_map>
+#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/types.hh"
#include "mem/request.hh"
#include "arch/pseudo_inst.hh"
#include "arch/utility.hh"
+#include "base/bitfield.hh"
#include "base/types.hh" // For Tick and Addr data types.
#include "debug/PseudoInst.hh"
#include "sim/guest_abi.hh"