cpu: Make automatic transition to OFF optional

Add the power_gating_on_idle option to control whether a core
automatically enters the power gated state. The default behaviour is
to transition to clock gated when idle, but not to power gated. When
this option is set to true, the core automatically transitions to the
power gated state after a configurable latency.

Change-Id: Ida98c7fc532de4140d0e511c25613769b47b3702
Reviewed-on: https://gem5-review.googlesource.com/5741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 0e131ae0ad5fa8f834d0f0823f7460fa74d54efe..1bf2c1e354234e3485303bcf8f39d8f673305917 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -138,6 +138,10 @@ class BaseCPU(MemObject):
     pwr_gating_latency = Param.Cycles(300,
         "Latency to enter power gating state when all contexts are suspended")
 
+    power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\
+        "to the OFF power state after all thread are disabled for "\
+        "pwr_gating_latency cycles")
+
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Tick to start function trace")
 

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 78cf4196cfe51bb640f43ef19acc3866c0b4ae85..af55ee1d6233950a186d898ba9a5e65821aebd0f 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -138,6 +138,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
       addressMonitor(p->numThreads),
       syscallRetryLatency(p->syscallRetryLatency),
       pwrGatingLatency(p->pwr_gating_latency),
+      powerGatingOnIdle(p->power_gating_on_idle),
       enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
 {
     // if Python did not provide a valid ID, do it here
@@ -493,7 +494,8 @@ BaseCPU::schedulePowerGatingEvent()
             return;
     }
 
-    if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED) {
+    if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED &&
+        powerGatingOnIdle) {
         assert(!enterPwrGatingEvent.scheduled());
         // Schedule a power gating event when clock gated for the specified
         // amount of time
@@ -536,8 +538,12 @@ BaseCPU::suspendContext(ThreadID thread_num)
     // All CPU threads suspended, enter lower power state for the CPU
     ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
 
-    //Schedule power gating event when clock gated for a configurable cycles
-    schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
+    // If pwrGatingLatency is set to 0 then this mechanism is disabled
+    if (powerGatingOnIdle) {
+        // Schedule power gating event when clock gated for pwrGatingLatency
+        // cycles
+        schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
+    }
 }
 
 void

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 7039fcfbc5375ea038a6fa30661a0a87c617ee07..13c56a945d27acf052acc2c0549f1b834879d4ad 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -588,10 +588,13 @@ class BaseCPU : public MemObject
     bool waitForRemoteGDB() const;
 
     Cycles syscallRetryLatency;
+
   // Enables CPU to enter power gating on a configurable cycle count
   protected:
-    const Cycles pwrGatingLatency;
     void enterPwrGating();
+
+    const Cycles pwrGatingLatency;
+    const bool powerGatingOnIdle;
     EventFunctionWrapper enterPwrGatingEvent;
 };