break;
case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
+ conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
+ conf->rsrc2 = value;
+ break;
+ case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
+ conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
+ conf->rsrc2 = value;
+ break;
+ case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
+ conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
+ conf->rsrc2 = value;
+ break;
+ case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
+ conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
+ conf->rsrc2 = value;
break;
case R_00B84C_COMPUTE_PGM_RSRC2:
conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
conf->rsrc2 = value;
break;
+ case R_00B8A0_COMPUTE_PGM_RSRC3:
+ conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
+ conf->rsrc3 = value;
+ break;
case R_0286CC_SPI_PS_INPUT_ENA:
conf->spi_ps_input_ena = value;
break;
struct ac_shader_config {
unsigned num_sgprs;
unsigned num_vgprs;
+ unsigned num_shared_vgprs; /* GFX10: number of VGPRs shared between half-waves */
unsigned spilled_sgprs;
unsigned spilled_vgprs;
unsigned lds_size; /* in HW allocation units; i.e 256 bytes on SI, 512 bytes on CI+ */
unsigned scratch_bytes_per_wave;
unsigned rsrc1;
unsigned rsrc2;
+ unsigned rsrc3;
};
void ac_parse_shader_binary_config(const char *data, size_t nbytes,