examples/anlogic/ now also output the SVF file.

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
index fa9424cd89e3827077b29648e14978601607c02e..97c978a15053d6e4070e9976462ae7fee374de3d 100644 (file)
--- a/examples/anlogic/.gitignore
+++ b/examples/anlogic/.gitignore
@@ -1,4 +1,7 @@
 demo.bit
 demo_phy.area
 full.v
-*.log
\ No newline at end of file
+*.log
+*.h
+*.tde
+*.svf

diff --git a/examples/anlogic/README b/examples/anlogic/README
index 99143cce07d380ac3be45f90e0b242f904790283..35d8e9cb16ebb2e96e195063a9d692e765145778 100644 (file)
--- a/examples/anlogic/README
+++ b/examples/anlogic/README
@@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo
 export TD_HOME=<TD Install Directory>
 
 then run "bash build.sh" in this directory.
-

diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
index db8c3b3478d68072e098b16fb32c54a04ec3028b..06db525c9a1136e76d6c296e87f57b3a39334953 100644 (file)
--- a/examples/anlogic/build.tcl
+++ b/examples/anlogic/build.tcl
@@ -8,4 +8,4 @@ pack
 place
 route
 report_area -io_info -file demo_phy.area
-bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
+bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000

diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
index c8fbaed3e6a334396f285436867ed2a3a77870da..ec802502e811cf38dae9fdc3472c732f779bbb3f 100644 (file)
--- a/examples/anlogic/demo.adc
+++ b/examples/anlogic/demo.adc
@@ -1,2 +1,2 @@
 set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
-set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
\ No newline at end of file
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED

diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
index a7edf4e375a66a861601601e9f730423e302281a..e17db771ea047113621efd27882fc514de2c4904 100644 (file)
--- a/examples/anlogic/demo.v
+++ b/examples/anlogic/demo.v
@@ -1,18 +1,18 @@
 module demo (
-    input wire CLK_IN,  
-    output wire R_LED 
+    input wire CLK_IN,
+    output wire R_LED
 );
     parameter time1 = 30'd12_000_000;
     reg led_state;
     reg [29:0] count;
-    
+
     always @(posedge CLK_IN)begin
         if(count == time1)begin
-            count<= 30'd0;     
+            count<= 30'd0;
             led_state <= ~led_state;
         end
         else
             count <= count + 1'b1;
     end
     assign R_LED = led_state;
-endmodule
\ No newline at end of file
+endmodule

diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
index 5687bcd315bf6455306630bd711cc96a88b4b955..cb396cc2b04d4ef3abb861c2ea67de3b16b5f808 100644 (file)
--- a/examples/anlogic/demo.ys
+++ b/examples/anlogic/demo.ys
@@ -1,3 +1,3 @@
 read_verilog demo.v
 synth_anlogic -top demo
-write_verilog full.v
\ No newline at end of file
+write_verilog full.v