Flatten specific parts of the designs

diff --git a/gram/simulation/simsoc.ys b/gram/simulation/simsoc.ys
index 35e11ea83c5bbd2cd5ffcd8bdd7e4bd155c6b922..bdd7d3ddc8235571bbfb3760c6ef9662275ac113 100644 (file)
--- a/gram/simulation/simsoc.ys
+++ b/gram/simulation/simsoc.ys
@@ -12,5 +12,9 @@ pmuxtree
 memory_collect
 extract_fa -v
 clean
+flatten \ub
+flatten \decoder
+flatten \arbiter
+flatten \sysclk
 opt -fine -full
 write_verilog -norename build_simsoc/top.v