Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * elf64-ppc.c: Rename powerxx to power10 throughout.
+
2020-05-11 Alan Modra <amodra@gmail.com>
PR 25961
. mtctr %r12
. bctr
- There are also ELFv1 powerxx variants of these stubs.
+ There are also ELFv1 power10 variants of these stubs.
ppc_stub_long_branch_notoc:
. pla %r12,dest@pcrel
. b dest
In cases where the high instructions would add zero, they are
omitted and following instructions modified in some cases.
- For example, a powerxx ppc_stub_plt_call_notoc might simplify down
+ For example, a power10 ppc_stub_plt_call_notoc might simplify down
to
. pld %r12,xxx@pcrel
. mtctr %r12
/* Whether calls are made via the PLT from NOTOC functions. */
unsigned int notoc_plt:1;
- /* Whether to use powerxx instructions in linkage stubs. */
- unsigned int powerxx_stubs:1;
+ /* Whether to use power10 instructions in linkage stubs. */
+ unsigned int power10_stubs:1;
/* Incremented every time we size stubs. */
unsigned int stub_iteration;
case R_PPC64_PLT_PCREL34:
case R_PPC64_PLT_PCREL34_NOTOC:
case R_PPC64_PCREL28:
- htab->powerxx_stubs = 1;
+ htab->power10_stubs = 1;
break;
default:
break;
}
static bfd_byte *
-build_powerxx_offset (bfd *abfd, bfd_byte *p, bfd_vma off, int odd,
+build_power10_offset (bfd *abfd, bfd_byte *p, bfd_vma off, int odd,
bfd_boolean load)
{
uint64_t insn;
}
static unsigned int
-size_powerxx_offset (bfd_vma off, int odd)
+size_power10_offset (bfd_vma off, int odd)
{
if (off - odd + (1ULL << 33) < 1ULL << 34)
return odd + 8;
}
static unsigned int
-num_relocs_for_powerxx_offset (bfd_vma off, int odd)
+num_relocs_for_power10_offset (bfd_vma off, int odd)
{
if (off - odd + (1ULL << 33) < 1ULL << 34)
return 1;
}
static Elf_Internal_Rela *
-emit_relocs_for_powerxx_offset (struct bfd_link_info *info,
+emit_relocs_for_power10_offset (struct bfd_link_info *info,
Elf_Internal_Rela *r, bfd_vma roff,
bfd_vma targ, bfd_vma off, int odd)
{
if (stub_entry->stub_type >= ppc_stub_plt_call_notoc)
{
- if (htab->powerxx_stubs)
+ if (htab->power10_stubs)
{
bfd_vma start = (stub_entry->stub_offset
+ stub_entry->group->stub_sec->output_offset
+ stub_entry->group->stub_sec->output_section->vma);
if (stub_entry->stub_type > ppc_stub_plt_call_notoc)
start += 4;
- size = 8 + size_powerxx_offset (off, start & 4);
+ size = 8 + size_power10_offset (off, start & 4);
}
else
size = 8 + size_offset (off - 8);
relp = p;
num_rel = 0;
- if (htab->powerxx_stubs)
+ if (htab->power10_stubs)
{
bfd_boolean load = stub_entry->stub_type >= ppc_stub_plt_call_notoc;
- p = build_powerxx_offset (htab->params->stub_bfd, p, off, odd, load);
+ p = build_power10_offset (htab->params->stub_bfd, p, off, odd, load);
}
else
{
if (info->emitrelocations)
{
bfd_vma roff = relp - stub_entry->group->stub_sec->contents;
- if (htab->powerxx_stubs)
- num_rel += num_relocs_for_powerxx_offset (off, odd);
+ if (htab->power10_stubs)
+ num_rel += num_relocs_for_power10_offset (off, odd);
else
{
num_rel += num_relocs_for_offset (off);
r = get_relocs (stub_entry->group->stub_sec, num_rel);
if (r == NULL)
return FALSE;
- if (htab->powerxx_stubs)
- r = emit_relocs_for_powerxx_offset (info, r, roff, targ, off, odd);
+ if (htab->power10_stubs)
+ r = emit_relocs_for_power10_offset (info, r, roff, targ, off, odd);
else
r = emit_relocs_for_offset (info, r, roff, targ, off);
if (stub_entry->stub_type == ppc_stub_long_branch_notoc
}
}
- if (!htab->powerxx_stubs
+ if (!htab->power10_stubs
&& htab->glink_eh_frame != NULL
&& htab->glink_eh_frame->size != 0)
{
if (info->emitrelocations)
{
unsigned int num_rel;
- if (htab->powerxx_stubs)
- num_rel = num_relocs_for_powerxx_offset (off, odd);
+ if (htab->power10_stubs)
+ num_rel = num_relocs_for_power10_offset (off, odd);
else
num_rel = num_relocs_for_offset (off - 8);
stub_entry->group->stub_sec->reloc_count += num_rel;
stub_entry->group->stub_sec->flags |= SEC_RELOC;
}
- if (htab->powerxx_stubs)
- extra = size_powerxx_offset (off, odd);
+ if (htab->power10_stubs)
+ extra = size_power10_offset (off, odd);
else
extra = size_offset (off - 8);
/* Include branch insn plus those in the offset sequence. */
calculated. */
off -= extra;
- if (!htab->powerxx_stubs)
+ if (!htab->power10_stubs)
{
/* After the bcl, lr has been modified so we need to emit
.eh_frame info saying the return address is in r12. */
if (info->emitrelocations)
{
unsigned int num_rel;
- if (htab->powerxx_stubs)
- num_rel = num_relocs_for_powerxx_offset (off, odd);
+ if (htab->power10_stubs)
+ num_rel = num_relocs_for_power10_offset (off, odd);
else
num_rel = num_relocs_for_offset (off - 8);
stub_entry->group->stub_sec->reloc_count += num_rel;
size = plt_stub_size (htab, stub_entry, off);
- if (!htab->powerxx_stubs)
+ if (!htab->power10_stubs)
{
/* After the bcl, lr has been modified so we need to emit
.eh_frame info saying the return address is in r12. */
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
+ renaming.
+ * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
+ place of -mfuture/-Mfuture.
+ * testsuite/gas/ppc/prefix-pcrel.d: Likewise.
+ * testsuite/gas/ppc/prefix-reloc.d: Likewise.
+
2020-05-06 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
insn_length = 4;
if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
insn_length = 2;
- else if ((opcode->flags & PPC_OPCODE_POWERXX) != 0
+ else if ((opcode->flags & PPC_OPCODE_POWER10) != 0
&& PPC_PREFIX_P (insn))
{
struct insn_label_list *l;
-#as: -mfuture
-#objdump: -dr -Mfuture
-#name: POWERXX alignment of labels test
+#as: -mpower10
+#objdump: -dr -Mpower10
+#name: POWER10 alignment of labels test
.*
-#as: -mfuture
-#objdump: -dr -Mfuture
-#name: POWERXX pcrel tests
+#as: -mpower10
+#objdump: -dr -Mpower10
+#name: POWER10 pcrel tests
.*
-#as: -a64 -mfuture
-#objdump: -dr -Mfuture
+#as: -a64 -mpower10
+#objdump: -dr -Mpower10
#name: Prefix insn relocations
.*
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * powerpc.cc: Rename powerxx to power10 throughout.
+
2020-05-02 H.J. Lu <hongjiu.lu@intel.com>
PR gold/25904
glink_(NULL), rela_dyn_(NULL), copy_relocs_(),
tlsld_got_offset_(-1U),
stub_tables_(), branch_lookup_table_(), branch_info_(), tocsave_loc_(),
- powerxx_stubs_(false), plt_thread_safe_(false), plt_localentry0_(false),
+ power10_stubs_(false), plt_thread_safe_(false), plt_localentry0_(false),
plt_localentry0_init_(false), has_localentry0_(false),
has_tls_get_addr_opt_(false),
relax_failed_(false), relax_fail_count_(0),
}
bool
- powerxx_stubs() const
- { return this->powerxx_stubs_; }
+ power10_stubs() const
+ { return this->power10_stubs_; }
void
- set_powerxx_stubs()
+ set_power10_stubs()
{
- this->powerxx_stubs_ = true;
+ this->power10_stubs_ = true;
}
bool
Branches branch_info_;
Tocsave_loc tocsave_loc_;
- bool powerxx_stubs_;
+ bool power10_stubs_;
bool plt_thread_safe_;
bool plt_localentry0_;
bool plt_localentry0_init_;
if (r_type == elfcpp::R_PPC64_REL24_NOTOC)
{
if (!p.second && !p.first->second.notoc_
- && !this->targ_->powerxx_stubs())
+ && !this->targ_->power10_stubs())
this->need_resize_ = true;
p.first->second.notoc_ = 1;
}
if (r_type == elfcpp::R_PPC64_REL24_NOTOC)
{
if (!p.second && !p.first->second.notoc_
- && !this->targ_->powerxx_stubs())
+ && !this->targ_->power10_stubs())
this->need_resize_ = true;
p.first->second.notoc_ = 1;
}
&& cs->second.r2save_
&& !cs->second.localentry0_)
|| (cs->second.notoc_
- && !this->targ_->powerxx_stubs()))
+ && !this->targ_->power10_stubs()))
calls.push_back(cs);
if (calls.size() > 1)
std::stable_sort(calls.begin(), calls.end(),
typedef typename Branch_stub_entries::const_iterator branch_iter;
std::vector<branch_iter> branches;
if (!this->long_branch_stubs_.empty()
- && !this->targ_->powerxx_stubs())
+ && !this->targ_->power10_stubs())
for (branch_iter bs = this->long_branch_stubs_.begin();
bs != this->long_branch_stubs_.end();
++bs)
template<bool big_endian>
static unsigned char*
-build_powerxx_offset(unsigned char* p, uint64_t off, uint64_t odd, bool load)
+build_power10_offset(unsigned char* p, uint64_t off, uint64_t odd, bool load)
{
uint64_t insn;
if (off - odd + (1ULL << 33) < 1ULL << 34)
if (p->second.r2save_)
bytes += 4;
- if (this->targ_->powerxx_stubs())
+ if (this->targ_->power10_stubs())
{
uint64_t from = this->stub_address() + p->second.off_ + bytes;
if (bytes > 8 * 4)
uint64_t off = p->first.dest_ - loc;
if (p->second.notoc_)
{
- if (this->targ_->powerxx_stubs())
+ if (this->targ_->power10_stubs())
{
Address odd = loc & 4;
if (off + (1 << 25) < 2 << 25)
if (off + (1 << 25) < 2 << 25)
return 4;
- if (!this->targ_->powerxx_stubs())
+ if (!this->targ_->power10_stubs())
*need_lt = true;
return 16;
}
unsigned char* p;
if (size == 64
- && this->targ_->powerxx_stubs())
+ && this->targ_->power10_stubs())
{
if (!this->plt_call_stubs_.empty())
{
Address plt_addr = pltoff + plt->address();
Address from = this->stub_address() + (p - oview);
Address delta = plt_addr - from;
- p = build_powerxx_offset<big_endian>(p, delta, from & 4, true);
+ p = build_power10_offset<big_endian>(p, delta, from & 4, true);
write_insn<big_endian>(p, mtctr_12);
p += 4;
if (!this->build_tls_opt_tail(p, cs))
if (bs->second.notoc_ || delta + (1 << 25) >= 2 << 25)
{
unsigned char* startp = p;
- p = build_powerxx_offset<big_endian>(p, delta, loc & 4, false);
+ p = build_power10_offset<big_endian>(p, delta, loc & 4, false);
delta -= p - startp;
}
if (delta + (1 << 25) < 2 << 25)
case elfcpp::R_PPC64_GOT_TLSLD34:
case elfcpp::R_PPC64_GOT_DTPREL34:
case elfcpp::R_PPC64_GOT_TPREL34:
- target->set_powerxx_stubs();
+ target->set_power10_stubs();
break;
default:
break;
case elfcpp::R_PPC64_GOT_TLSLD34:
case elfcpp::R_PPC64_GOT_DTPREL34:
case elfcpp::R_PPC64_GOT_TPREL34:
- target->set_powerxx_stubs();
+ target->set_power10_stubs();
break;
default:
break;
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * elf/ppc64.h: Update comment.
+ * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
+
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add
RELOC_NUMBER (R_PPC64_PLTSEQ, 119)
RELOC_NUMBER (R_PPC64_PLTCALL, 120)
-/* Powerxx support. */
+/* Power10 support. */
RELOC_NUMBER (R_PPC64_PLTSEQ_NOTOC, 121)
RELOC_NUMBER (R_PPC64_PLTCALL_NOTOC, 122)
RELOC_NUMBER (R_PPC64_PCREL_OPT, 123)
/* Opcode is supported by EFS2. */
#define PPC_OPCODE_EFS2 0x200000000000ull
-/* Opcode is only supported by powerxx architecture. */
-#define PPC_OPCODE_POWERXX 0x400000000000ull
+/* Opcode is only supported by power10 architecture. */
+#define PPC_OPCODE_POWER10 0x400000000000ull
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
+ place of -mfuture/-Mfuture.
+ * testsuite/ld-powerpc/notoc2.d: Likewise.
+ * testsuite/ld-powerpc/powerpc.exp: Likewise.
+ * testsuite/ld-powerpc/tlsgd.d: Likewise.
+ * testsuite/ld-powerpc/tlsie.d: Likewise.
+ * testsuite/ld-powerpc/tlsld.d: Likewise.
+
2020-05-11 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
-#as: -a64 -mfuture
+#as: -a64 -mpower10
#ld: -melf64ppc -shared --plt-align=0 --hash-style=gnu
-#objdump: -dr -Mfuture
+#objdump: -dr -Mpower10
.*
#source: notoc2.s
-#as: -a64 -mfuture
+#as: -a64 -mpower10
#ld: -shared -z norelro
-#objdump: -d -Mfuture
+#objdump: -d -Mpower10
#target: powerpc64*-*-*
.*
{"notoc ext" "" "" "-a64" {ext.s} {} ""}
{"notoc" "-melf64ppc --no-plt-localentry -T ext.lnk" "" "-a64" {notoc.s}
{{objdump -d notoc.d} {readelf {-wf -W} notoc.wf}} "notoc"}
- {"notoc2" "-melf64ppc -shared" "" "-a64 -mfuture" {notoc2.s}
- {{objdump {-d -Mfuture} notoc2.d}} "notoc2"}
+ {"notoc2" "-melf64ppc -shared" "" "-a64 -mpower10" {notoc2.s}
+ {{objdump {-d -Mpower10} notoc2.d}} "notoc2"}
{"pcrelopt" "-melf64ppc --hash-style=gnu" "tmpdir/symtocbase.so"
- "-a64 -mfuture" {pcrelopt.s}
- {{objdump {-d -Mfuture} pcrelopt.d}
+ "-a64 -mpower10" {pcrelopt.s}
+ {{objdump {-d -Mpower10} pcrelopt.d}
{readelf {-S --wide} pcrelopt.sec}} "pcrelopt" }
}
#source: tlsgd.s
-#as: -a64 -mfuture
+#as: -a64 -mpower10
#ld: -melf64ppc
-#objdump: -dr -Mfuture
+#objdump: -dr -Mpower10
.*: file format .*
#source: tlsie.s
-#as: -a64 -mfuture
+#as: -a64 -mpower10
#ld: -melf64ppc
-#objdump: -dr -Mfuture
+#objdump: -dr -Mpower10
.*: file format .*
#source: tlsld.s
-#as: -a64 -mfuture
+#as: -a64 -mpower10
#ld: -melf64ppc
-#objdump: -dr -Mfuture
+#objdump: -dr -Mpower10
.*: file format .*
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add "power10" entry.
+ (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
+ * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
+
2020-05-11 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
+ { "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+ 0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
- | PPC_OPCODE_POWERXX | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
{ "ppc", PPC_OPCODE_PPC,
0 },
/* Get the major opcode of the insn. */
opcode = NULL;
- if ((dialect & PPC_OPCODE_POWERXX) != 0
+ if ((dialect & PPC_OPCODE_POWER10) != 0
&& PPC_OP (insn) == 0x1)
{
uint64_t temp_insn, suffix;
#define POWER7 PPC_OPCODE_POWER7
#define POWER8 PPC_OPCODE_POWER8
#define POWER9 PPC_OPCODE_POWER9
-#define POWERXX PPC_OPCODE_POWERXX
+#define POWER10 PPC_OPCODE_POWER10
#define CELL PPC_OPCODE_CELL
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
The format of this opcode table is the same as the main opcode table. */
const struct powerpc_opcode prefix_opcodes[] = {
-{"pnop", PMRR, PREFIX_MASK, POWERXX, 0, {0}},
-{"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWERXX, 0, {RT, SI34}},
-{"paddi", PMLS|OP(14), P_D_MASK, POWERXX, 0, {RT, RA0, SI34, PCREL0}},
-{"psubi", PMLS|OP(14), P_D_MASK, POWERXX, 0, {RT, RA0, NSI34, PCREL0}},
-{"pla", PMLS|OP(14), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"plwz", PMLS|OP(32), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"plbz", PMLS|OP(34), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"pstw", PMLS|OP(36), P_D_MASK, POWERXX, 0, {RS, D34, PRA0, PCREL}},
-{"pstb", PMLS|OP(38), P_D_MASK, POWERXX, 0, {RS, D34, PRA0, PCREL}},
-{"plhz", PMLS|OP(40), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"plwa", P8LS|OP(41), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"plxsd", P8LS|OP(42), P_D_MASK, POWERXX, 0, {VD, D34, PRA0, PCREL}},
-{"plha", PMLS|OP(42), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"plxssp", P8LS|OP(43), P_D_MASK, POWERXX, 0, {VD, D34, PRA0, PCREL}},
-{"psth", PMLS|OP(44), P_D_MASK, POWERXX, 0, {RS, D34, PRA0, PCREL}},
-{"pstxsd", P8LS|OP(46), P_D_MASK, POWERXX, 0, {VS, D34, PRA0, PCREL}},
-{"pstxssp", P8LS|OP(47), P_D_MASK, POWERXX, 0, {VS, D34, PRA0, PCREL}},
-{"plfs", PMLS|OP(48), P_D_MASK, POWERXX, 0, {FRT, D34, PRA0, PCREL}},
-{"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWERXX, 0, {XTOP, D34, PRA0, PCREL}},
-{"plfd", PMLS|OP(50), P_D_MASK, POWERXX, 0, {FRT, D34, PRA0, PCREL}},
-{"pstfs", PMLS|OP(52), P_D_MASK, POWERXX, 0, {FRS, D34, PRA0, PCREL}},
-{"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWERXX, 0, {XTOP, D34, PRA0, PCREL}},
-{"pstfd", PMLS|OP(54), P_D_MASK, POWERXX, 0, {FRS, D34, PRA0, PCREL}},
-{"plq", P8LS|OP(56), P_D_MASK, POWERXX, 0, {RTQ, D34, PRAQ, PCREL}},
-{"pld", P8LS|OP(57), P_D_MASK, POWERXX, 0, {RT, D34, PRA0, PCREL}},
-{"pstq", P8LS|OP(60), P_D_MASK, POWERXX, 0, {RSQ, D34, PRA0, PCREL}},
-{"pstd", P8LS|OP(61), P_D_MASK, POWERXX, 0, {RS, D34, PRA0, PCREL}},
+{"pnop", PMRR, PREFIX_MASK, POWER10, 0, {0}},
+{"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWER10, 0, {RT, SI34}},
+{"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL0}},
+{"psubi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, NSI34, PCREL0}},
+{"pla", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
+{"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
+{"plhz", PMLS|OP(40), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"plwa", P8LS|OP(41), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"plxsd", P8LS|OP(42), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}},
+{"plha", PMLS|OP(42), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"plxssp", P8LS|OP(43), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}},
+{"psth", PMLS|OP(44), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
+{"pstxsd", P8LS|OP(46), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}},
+{"pstxssp", P8LS|OP(47), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}},
+{"plfs", PMLS|OP(48), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}},
+{"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}},
+{"plfd", PMLS|OP(50), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}},
+{"pstfs", PMLS|OP(52), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}},
+{"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}},
+{"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}},
+{"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}},
+{"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
+{"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
+{"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
};
const unsigned int prefix_num_opcodes =
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