Add README and LICENSE

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+Copyright (C) 2020 LambdaConcept
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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+# A framework for building SoCs with nMigen
+
+**LambdaSoC is a work in progress. Please keep in mind that some interfaces will undergo breaking changes as they evolve and/or get moved [upstream][nmigen-soc].**
+
+## Installation
+
+```
+git clone https://github.com/lambdaconcept/lambdasoc
+git submodule update --init --recursive
+
+pip install git+https://github.com/nmigen/nmigen-soc
+pip install git+https://github.com/nmigen/nmigen-stdio
+pip install git+https://github.com/nmigen/nmigen-boards
+pip install git+https://github.com/lambdaconcept/minerva
+pip install git+https://github.com/m-labs/asyncserial
+
+python setup.py install
+```
+
+## Quick start
+
+Let's build and run the SoC example at [examples/sram_soc.py][sram_soc]. It is composed of a [Minerva][minerva] CPU, SRAM storage, an UART and a timer.
+
+##### Requirements
+* A `riscv64-unknown-elf` GNU toolchain, to build the first-stage bootloader
+* A [supported platform][nmigen-boards] with enough resources to fit the SoC
+
+Here, we build the SoC for the `nmigen_boards.arty_a7.ArtyA7Platform`:
+```
+python examples/sram_soc.py --baudrate=9600 nmigen_boards.arty_a7.ArtyA7Platform
+```
+
+The bootloader shell can be accessed from the serial port:
+```
+flterm --speed=9600 /dev/ttyUSB1
+
+LambdaSoC BIOS
+(c) Copyright 2007-2020 M-Labs Limited
+(c) Copyright 2020 LambdaConcept
+Built Mar 26 2020 13:41:04
+
+BIOS CRC passed (c402e7e2)
+BIOS>
+```
+
+The `help` command lists available commands.
+
+## License
+
+LambdaSoC is released under the permissive two-clause BSD license. See LICENSE file for full copyright and license information.
+
+[nmigen-soc]: https://github.com/nmigen/nmigen-soc
+[minerva]: https://github.com/lambdaconcept/minerva
+[nmigen-boards]: https://github.com/nmigen/nmigen-boards
+[sram_soc]: https://github.com/lambdaconcept/lambdasoc/blob/master/examples/sram_soc.py