Match CR size on ISACaller mtcrf test case

The underlying register for CR seems to be 64 bits for some reason. See:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=2f9dfa8746625f74fccaf9cd8a86f5503837009d;hb=HEAD#l495

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index 00856352cef7f93b49c11f34264c3c162a8b5e37..ce934609b23be8199a010d9eb51ac3c2564ce8be 100644 (file)
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -317,7 +317,7 @@ class DecoderTestCase(FHDLTestCase):
             print("cr%d", sim.crl[i])
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
             # check CR itself
-            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
+            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = run_tst(prog, initial_regs)