CP15 c15: enable execution with accesses to c15 registers

Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 4a92005043cf3e1ed0a7f5c1b5932857e839393e..54482864a34e07125234af9efeb39895335cdfc2 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
           case MISCREG_L2LATENCY:
             return new WarnUnimplemented(
                     isRead ? "mrc l2latency" : "mcr l2latency", machInst);
+          case MISCREG_CRN15:
+            return new WarnUnimplemented(
+                    isRead ? "mrc crn15" : "mcr crn15", machInst);
 
             // Write only.
           case MISCREG_TLBIALLIS:

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 1fecaa38d65368896da85303fd6312dacf6a1afd..db097c653e3474356e87103f610e7dd43502ab4a 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -463,7 +463,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         break;
       case 15:
         // Implementation defined
-        break;
+        return MISCREG_CRN15;
     }
     // Unrecognized register
     return NUM_MISCREGS;

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f99748622eb905a37187b156876ee926d94a111b..5e5735de7e6fea00398b41e27034f12a71322b83 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -196,6 +196,7 @@ namespace ArmISA
         MISCREG_ISR,
         MISCREG_FCEIDR,
         MISCREG_L2LATENCY,
+        MISCREG_CRN15,
 
 
         MISCREG_CP15_END,
@@ -249,6 +250,7 @@ namespace ArmISA
         "dccmvau",
         "nsacr",
         "vbar", "mvbar", "isr", "fceidr", "l2latency",
+        "crn15",
         "nop", "raz"
     };