examples: rename clkdiv/ctrl to ctr/ctr_ce.

diff --git a/examples/clkdiv.py b/examples/clkdiv.py
deleted file mode 100644 (file)
index 7be26b6..0000000
--- a/examples/clkdiv.py
+++ /dev/null
@@ -1,26 +0,0 @@
-from nmigen import *
-from nmigen.back import rtlil, verilog, pysim
-
-
-class ClockDivisor:
-    def __init__(self, factor):
-        self.v = Signal(factor, reset=2**factor-1)
-        self.o = Signal()
-
-    def get_fragment(self, platform):
-        m = Module()
-        m.d.sync += self.v.eq(self.v + 1)
-        m.d.comb += self.o.eq(self.v[-1])
-        return m.lower(platform)
-
-
-ctr  = ClockDivisor(factor=16)
-frag = ctr.get_fragment(platform=None)
-
-# print(rtlil.convert(frag, ports=[ctr.o]))
-print(verilog.convert(frag, ports=[ctr.o]))
-
-with pysim.Simulator(frag,
-        vcd_file=open("clkdiv.vcd", "w")) as sim:
-    sim.add_clock(1e-6)
-    sim.run_until(100e-6, run_passive=True)

diff --git a/examples/ctr.py b/examples/ctr.py
new file mode 100644 (file)
index 0000000..be1bb09
--- /dev/null
+++ b/examples/ctr.py
@@ -0,0 +1,26 @@
+from nmigen import *
+from nmigen.back import rtlil, verilog, pysim
+
+
+class Counter:
+    def __init__(self, width):
+        self.v = Signal(width, reset=2**width-1)
+        self.o = Signal()
+
+    def get_fragment(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m.lower(platform)
+
+
+ctr  = Counter(width=16)
+frag = ctr.get_fragment(platform=None)
+
+# print(rtlil.convert(frag, ports=[ctr.o]))
+print(verilog.convert(frag, ports=[ctr.o]))
+
+with pysim.Simulator(frag,
+        vcd_file=open("ctr.vcd", "w")) as sim:
+    sim.add_clock(1e-6)
+    sim.run_until(100e-6, run_passive=True)

diff --git a/examples/ctr_ce.py b/examples/ctr_ce.py
new file mode 100644 (file)
index 0000000..244c428
--- /dev/null
+++ b/examples/ctr_ce.py
@@ -0,0 +1,37 @@
+from nmigen import *
+from nmigen.back import rtlil, verilog, pysim
+
+
+class Counter:
+    def __init__(self, width):
+        self.v = Signal(width, reset=2**width-1)
+        self.o = Signal()
+        self.ce = Signal()
+
+    def get_fragment(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return CEInserter(self.ce)(m.lower(platform))
+
+
+ctr  = Counter(width=16)
+frag = ctr.get_fragment(platform=None)
+
+# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
+print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
+
+with pysim.Simulator(frag,
+        vcd_file=open("ctrl.vcd", "w"),
+        gtkw_file=open("ctrl.gtkw", "w"),
+        traces=[ctr.ce, ctr.v, ctr.o]) as sim:
+    sim.add_clock(1e-6)
+    def ce_proc():
+        yield; yield; yield
+        yield ctr.ce.eq(1)
+        yield; yield; yield
+        yield ctr.ce.eq(0)
+        yield; yield; yield
+        yield ctr.ce.eq(1)
+    sim.add_sync_process(ce_proc())
+    sim.run_until(100e-6, run_passive=True)

diff --git a/examples/ctrl.py b/examples/ctrl.py
deleted file mode 100644 (file)
index fa9cf44..0000000
--- a/examples/ctrl.py
+++ /dev/null
@@ -1,37 +0,0 @@
-from nmigen import *
-from nmigen.back import rtlil, verilog, pysim
-
-
-class ClockDivisor:
-    def __init__(self, factor):
-        self.v = Signal(factor, reset=2**factor-1)
-        self.o = Signal()
-        self.ce = Signal()
-
-    def get_fragment(self, platform):
-        m = Module()
-        m.d.sync += self.v.eq(self.v + 1)
-        m.d.comb += self.o.eq(self.v[-1])
-        return CEInserter(self.ce)(m.lower(platform))
-
-
-ctr  = ClockDivisor(factor=16)
-frag = ctr.get_fragment(platform=None)
-
-# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
-print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
-
-with pysim.Simulator(frag,
-        vcd_file=open("ctrl.vcd", "w"),
-        gtkw_file=open("ctrl.gtkw", "w"),
-        traces=[ctr.ce, ctr.v, ctr.o]) as sim:
-    sim.add_clock(1e-6)
-    def ce_proc():
-        yield; yield; yield
-        yield ctr.ce.eq(1)
-        yield; yield; yield
-        yield ctr.ce.eq(0)
-        yield; yield; yield
-        yield ctr.ce.eq(1)
-    sim.add_sync_process(ce_proc())
-    sim.run_until(100e-6, run_passive=True)