Adds is_wire to SigBit and SigChunk

Useful for PYOSYS because Python can't easily check wire against NULL.

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4dad3c428739ccf96baacc708fe27d933a39e436..a5f170085ced561caca6f6f123aa0fc22b066493 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -735,6 +735,7 @@ struct RTLIL::SigChunk
 
        RTLIL::SigChunk extract(int offset, int length) const;
        inline int size() const { return width; }
+       inline int is_wire() const { return wire != NULL; }
 
        bool operator <(const RTLIL::SigChunk &other) const;
        bool operator ==(const RTLIL::SigChunk &other) const;
@@ -760,6 +761,8 @@ struct RTLIL::SigBit
        SigBit(const RTLIL::SigBit &sigbit) = default;
        RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
 
+       inline int is_wire() const { return wire != NULL; }
+
        bool operator <(const RTLIL::SigBit &other) const;
        bool operator ==(const RTLIL::SigBit &other) const;
        bool operator !=(const RTLIL::SigBit &other) const;