X86: Implement the ldst microop and put it in existing microcode where appropriate.

--HG--
extra : convert_revision : f08bd725d07a501bb7a0ce91590b5d37db99c6f3

diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 0679e972b49022c9885851b8ff1101ed4dd68c06..6724ea9b0730f6024f895d0ff802af7b2981429b 100644 (file)
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -145,6 +145,7 @@ output exec {{
 
 #include <cmath>
 #include "arch/x86/miscregs.hh"
+#include "arch/x86/tlb.hh"
 #include "base/bigint.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"

diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 1bdc1d37a8878c56aa338757ac86682232a99e98..106a8a0fe681a11514e78330618c0b1d87d1515a 100644 (file)
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -123,7 +123,7 @@ def template MicroLoadExecute {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, 0);
+        fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
 
         if(fault == NoFault)
         {
@@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, 0);
+        fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment));
 
         return fault;
     }
@@ -197,7 +197,7 @@ def template MicroStoreExecute {{
 
         if(fault == NoFault)
         {
-            fault = write(xc, Mem, EA, 0);
+            fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
             if(fault == NoFault)
             {
                 %(op_wb)s;
@@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{
 
         if(fault == NoFault)
         {
-            fault = write(xc, Mem, EA, 0);
+            fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment));
             if(fault == NoFault)
             {
                 %(op_wb)s;
@@ -358,7 +358,7 @@ let {{
 
     calculateEA = "EA = SegBase + scale * Index + Base + disp;"
 
-    def defineMicroLoadOp(mnemonic, code):
+    def defineMicroLoadOp(mnemonic, code, mem_flags=0):
         global header_output
         global decoder_output
         global exec_output
@@ -368,7 +368,9 @@ let {{
 
         # Build up the all register version of this micro op
         iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
-                {"code": code, "ea_code": calculateEA})
+                {"code": code,
+                 "ea_code": calculateEA,
+                 "mem_flags": mem_flags})
         header_output += MicroLdStOpDeclare.subst(iop)
         decoder_output += MicroLdStOpConstructor.subst(iop)
         exec_output += MicroLoadExecute.subst(iop)
@@ -386,9 +388,10 @@ let {{
         microopClasses[name] = LoadOp
 
     defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
+    defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'StoreCheck')
     defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
 
-    def defineMicroStoreOp(mnemonic, code):
+    def defineMicroStoreOp(mnemonic, code, mem_flags=0):
         global header_output
         global decoder_output
         global exec_output
@@ -398,7 +401,9 @@ let {{
 
         # Build up the all register version of this micro op
         iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
-                {"code": code, "ea_code": calculateEA})
+                {"code": code,
+                 "ea_code": calculateEA,
+                 "mem_flags": mem_flags})
         header_output += MicroLdStOpDeclare.subst(iop)
         decoder_output += MicroLdStOpConstructor.subst(iop)
         exec_output += MicroStoreExecute.subst(iop)
@@ -419,7 +424,9 @@ let {{
     defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
 
     iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
-            {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA})
+            {"code": "Data = merge(Data, EA, dataSize);",
+             "ea_code": calculateEA,
+             "mem_flags": 0})
     header_output += MicroLeaDeclare.subst(iop)
     decoder_output += MicroLdStOpConstructor.subst(iop)
     exec_output += MicroLeaExecute.subst(iop)

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 386d1635dddf184f4c8b744da1d1bdcebcf5a6af..24373c6232885d7b71b606d346755abd94753ed5 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -62,6 +62,7 @@
 
 #if FULL_SYSTEM
 
+#include "arch/segmentregs.hh"
 #include "mem/request.hh"
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
@@ -73,6 +74,8 @@ class Packet;
 
 namespace X86ISA
 {
+    static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+
     struct TlbEntry
     {
         Addr pageStart;
@@ -134,6 +137,7 @@ class DTB : public TLB
 
 #include <iostream>
 
+#include "arch/x86/segmentregs.hh"
 #include "sim/host.hh"
 #include "sim/tlb.hh"
 
@@ -141,6 +145,8 @@ class Checkpoint;
 
 namespace X86ISA
 {
+    static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+
     struct TlbEntry
     {
         Addr pageStart;