go with separate bit for Pack/Unpack mode in SVP64RMModeDecode

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index f5da27b4d70cecd47631b3335edd70579c64042b..8f0ea054682f3fcb24ce08ae8287c0578530e11a 100644 (file)
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -241,7 +241,9 @@ class SVP64MODEb(_Const):
     # mode bits
     MOD2_MSB = 0
     MOD2_LSB = 1
-    LDST_SHIFT = 2 # set =1 for shift mode
+    # pack detection (TODO, CR-ops needs one of these too)
+    LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode
+    ARITH_PACK = 4 # set =1 for Arithmetic Pack mode
     # when predicate not set: 0=ignore/skip 1=zero
     DZ = 3  # for destination
     SZ = 4  # for source
@@ -339,5 +341,6 @@ class XERRegsEnum:
     OV=2 # OV and OV32
     N_REGS = 3 # maximum number of regs
 
+
 if __name__ == '__main__':
     print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 03333548b4ffb343e87bcd8dd3a5463f56df9829..d5ffffab88179f805ef65015216fe6f799a00773 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -197,7 +197,6 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
     BRANCH = 5
-    PACK = 6
 
 
 @unique
@@ -257,7 +256,6 @@ class SVP64LDSTmode(Enum):
     INDEXED = 1
     ELSTRIDE = 2
     UNITSTRIDE = 3
-    SHIFT = 4
 
 
 # supported instructions: make sure to keep up-to-date with CSV files

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 4f6d65c35a9d02a4de1e2796290fc18ea4ecc460..cb7a620d16a5a90a7bfff424a0c9b21d488f3273 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -121,6 +121,7 @@ class SVP64RMModeDecode(Elaboratable):
         self.pred_dz = Signal(1) # predicate dest zeroing
 
         # Modes n stuff
+        self.pack_unpack = Signal(1) # pack/unpack mode
         self.saturate = Signal(SVP64sat)
         self.RC1 = Signal()
         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
@@ -163,13 +164,18 @@ class SVP64RMModeDecode(Elaboratable):
             comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])
 
         with m.Else():
+            pu = self.pack_unpack
             # combined arith / ldst decoding due to similarity
             with m.Switch(mode2):
                 with m.Case(0): # needs further decoding (LDST no mapreduce)
                     with m.If(is_ldst):
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
+                        comb += pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode
                     with m.Elif(mode[SVP64MODE.REDUCE]):
                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
+                        # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
+                        with m.If(self.rm_in.subvl != Const(0, 2)): # active
+                            comb += pu.eq(mode[SVP64MODE.ARITH_PACK])
                     with m.Else():
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
                 with m.Case(1):
@@ -237,11 +243,8 @@ class SVP64RMModeDecode(Elaboratable):
                         with m.If(self.rc_in):
                             comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED])
 
-                # Shifted Mode
-                with m.If(mode[SVP64MODE.LDST_SHIFT]):
-                    comb += self.ldstmode.eq(SVP64LDSTmode.SHIFT)
                 # RA is vectorised
-                with m.Elif(self.ldst_ra_vec):
+                with m.If(self.ldst_ra_vec):
                     comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED)
                 # not element-strided, therefore unit...
                 with m.Elif(~els):