i965: Move the destination reg setup for 8/16 wide to the emit code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 718b3800423c27710d5fb1667faab3686814066a..d535f51437a019fbee54203a703b09bf7c2f808a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -856,7 +856,6 @@ void brw_ff_sync(struct brw_compile *p,
 
 void brw_fb_WRITE(struct brw_compile *p,
                  int dispatch_width,
-                  struct brw_reg dest,
                   GLuint msg_reg_nr,
                   struct brw_reg src0,
                   GLuint binding_table_index,

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 71485cd1f71d8b31a0ce9603e6bef4ac1df09e2f..859068ec4eb884f57b9ba338a7c412c4f4135834 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1871,7 +1871,6 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
 
 void brw_fb_WRITE(struct brw_compile *p,
                  int dispatch_width,
-                  struct brw_reg dest,
                   GLuint msg_reg_nr,
                   struct brw_reg src0,
                   GLuint binding_table_index,
@@ -1883,6 +1882,12 @@ void brw_fb_WRITE(struct brw_compile *p,
    struct intel_context *intel = &p->brw->intel;
    struct brw_instruction *insn;
    GLuint msg_control, msg_type;
+   struct brw_reg dest;
+
+   if (dispatch_width == 16)
+      dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
+   else
+      dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
 
    if (intel->gen >= 6 && binding_table_index == 0) {
       insn = next_insn(p, BRW_OPCODE_SENDC);

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5426925e372ea2f2345efc28ce23a5b0b48552b7..44eb1be51083dac6b4b6b9ab81e2d4a22b6c6816 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2145,7 +2145,6 @@ fs_visitor::generate_fb_write(fs_inst *inst)
 
    brw_fb_WRITE(p,
                8, /* dispatch_width */
-               retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
                inst->base_mrf,
                implied_header,
                inst->target,

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index cdc1f367e5c3aab092c9a064c5d2e48f78cf8a7d..0b136a81ab733f81d62b89195a3c8c7e9b0478a3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1325,12 +1325,6 @@ static void fire_fb_write( struct brw_wm_compile *c,
 {
    struct brw_compile *p = &c->func;
    struct intel_context *intel = &p->brw->intel;
-   struct brw_reg dst;
-
-   if (c->dispatch_width == 16)
-      dst = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
-   else
-      dst = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
 
    /* Pass through control information:
     * 
@@ -1352,7 +1346,6 @@ static void fire_fb_write( struct brw_wm_compile *c,
 /*  send (16) null.0<1>:uw m0               r0.0<8;8,1>:uw   0x85a04000:ud    { Align1 EOT } */
    brw_fb_WRITE(p,
                c->dispatch_width,
-               dst,
                base_reg,
                retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
                target,