soc/cores/cpu/vexriscv: set default variant to None in add_sources

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index b79a7fd6c9e260329a8fa7a0354006dff8f6838c..e7b18bf647a2721d667f896db07e8f5715a34332 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -66,7 +66,7 @@ class LM32(Module):
         self.add_sources(platform, variant)
 
     @staticmethod
-    def add_sources(platform, variant):
+    def add_sources(platform, variant=None):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir, "submodule", "rtl"),