add in use of inc_offs and sub-src/dest offsets

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index c73e3fde29e0cc4be104bc3235befac54ccb7581..4766a821e089f1690cb2be07faacf53b62ad8c35 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -45,8 +45,10 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   // in a stack of other things that are needed.
   insn_bits_t bits = s_insn.bits();
   int vlen = 0;
+  int subvl = 0;
   if (p->get_state()->prv == 0) { // XXX HACK - disable in supervisor mode
     vlen = p->get_state()->sv().vl;
+    subvl = p->get_state()->sv().subvl;
   }
   // need to know if register is used as float or int.
   // REGS_PATTERN is generated by id_regs.py (per opcode)
@@ -55,12 +57,14 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t dest_pred = ~0x0;
   bool dest_pset = false;
   int *dest_offs = &(p->get_state()->sv().destoffs);
+  int *sub_doffs = &(p->get_state()->sv().dsvoffs);
   bool zeroing = false;
 #ifdef INSN_CATEGORY_TWINPREDICATION
   reg_t src_preg = 0;
   reg_t src_pred = ~0x0;
   bool src_pset = false;
   int *src_offs = &(p->get_state()->sv().srcoffs);
+  int *ssv_offs = &(p->get_state()->sv().ssvoffs);
   bool zeroingsrc = false;
 #endif
 #ifdef INSN_TYPE_BRANCH
@@ -176,7 +180,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
     {
       while ((src_pset = (src_pred & (1<<pred_remap(src_preg, *src_offs))))
                         == 0) {
-          *src_offs += 1;
+          inc_offs(vlen, subvl, *src_offs, *ssv_offs);
           if (*src_offs >= vlen) {
               break;
           }
@@ -186,7 +190,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
     {
       while ((dest_pset = (dest_pred & (1<<pred_remap(dest_preg, *dest_offs))))
                         == 0) {
-          *dest_offs += 1;
+          inc_offs(vlen, subvl, *dest_offs, *sub_doffs);
           if (*dest_offs >= vlen) {
               break;
           }
@@ -278,9 +282,9 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
         break;
       }
 #ifdef INSN_CATEGORY_TWINPREDICATION
-      *src_offs += 1;
+      inc_offs(vlen, subvl, *src_offs, *ssv_offs);
 #endif
-      *dest_offs += 1;
+      inc_offs(vlen, subvl, *dest_offs, *sub_doffs);
   }
 #ifdef INSN_TYPE_BRANCH
   // ok, at the end of the loop, if the predicates are equal,