* config/rs6000/rs6000.md ('type' attribute): Add
veclogical,veccmpfx,vecexts,vecmove insn types.
(*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
(*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
*nabs<mode>2_hw): Change type to vecmove.
(*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
*boolcc<mode>3_internal, *eqv<mode>3_internal,
*one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
*ieee_128bit_vsx_abs<mode>2_internal,
*ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
*ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
*ieee128_mtvsrd_32bit): Change type to veclogical.
(mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
*movdi_internal32, *movdi_internal64): Update insn types.
* config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
vsx_extract_<mode>): Change type to veclogical.
(*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
(vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
*vsx_sign_extend_si_v2di): Change type to vecexts.
* config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
type to veclogical.
(*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
*altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
*altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx.
(*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
* config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
* config/rs6000/40x.md (ppc405-float): Add fpsimple.
* config/rs6000/440.md (ppc440-fp): Add fpsimple.
* config/rs6000/476.md (ppc476-fp): Add fpsimple.
* config/rs6000/601.md (ppc601-fp): Add fpsimple.
* config/rs6000/603.md (ppc603-fp): Add fpsimple.
* config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
* config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
(ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
(ppc7450-vecsimple): Add veclogical, vecmove.
(ppc7450-veccmp): Add veccmpfx.
* config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical,
vecmove.
(ppc8540_vector_compare): Add veccmpfx.
* config/rs6000/a2.md (ppca2-fp): Add fpsimple.
* config/rs6000/cell.md (cell-fp): Add fpsimple.
(cell-vecsimple): Add veclogical, vecmove.
(cell-veccmp): Add veccmpfx.
* config/rs6000/
e300c2c3.md (ppce300c3_fp): Add fpsimple.
* config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove,
veccmpfx.
* config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
* config/rs6000/power4.md (power4-fp): Add fpsimple.
(power4-vecsimple): Add veclogical, vecmove.
(power4-veccmp): Add veccmpfx.
* config/rs6000/power5.md (power5-fp): Add fpsimple.
* config/rs6000/power6.md (power6-fp): Add fpsimple.
(power6-vecsimple): Add veclogical, vecmove.
(power6-veccmp): Add veccmpfx.
* config/rs6000/power7.md (power7-fp): Add fpsimple.
(power7-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/power8.md (power8-fp): Add fpsimple.
(power8-vecsimple): Add veclogical, vecmove, veccmpfx.
* config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
* config/rs6000/titan.md (titan_fp): Add fpsimple.
* config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
fpsimple.
* config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.
From-SVN: r237812
+2016-06-27 Pat Haugen <pthaugen@us.ibm.com>
+
+ * config/rs6000/rs6000.md ('type' attribute): Add
+ veclogical,veccmpfx,vecexts,vecmove insn types.
+ (*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
+ copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
+ p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
+ (*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
+ *nabs<mode>2_hw): Change type to vecmove.
+ (*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
+ *boolcc<mode>3_internal, *eqv<mode>3_internal,
+ *one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
+ *ieee_128bit_vsx_abs<mode>2_internal,
+ *ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
+ *ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
+ *ieee128_mtvsrd_32bit): Change type to veclogical.
+ (mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
+ *movdi_internal32, *movdi_internal64): Update insn types.
+ * config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
+ vsx_extract_<mode>): Change type to veclogical.
+ (*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
+ (vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
+ *vsx_sign_extend_si_v2di): Change type to vecexts.
+ * config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
+ type to veclogical.
+ (*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
+ *altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
+ *altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx.
+ (*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
+ * config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
+ negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
+ * config/rs6000/40x.md (ppc405-float): Add fpsimple.
+ * config/rs6000/440.md (ppc440-fp): Add fpsimple.
+ * config/rs6000/476.md (ppc476-fp): Add fpsimple.
+ * config/rs6000/601.md (ppc601-fp): Add fpsimple.
+ * config/rs6000/603.md (ppc603-fp): Add fpsimple.
+ * config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
+ * config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
+ (ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
+ (ppc7450-vecsimple): Add veclogical, vecmove.
+ (ppc7450-veccmp): Add veccmpfx.
+ * config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical,
+ vecmove.
+ (ppc8540_vector_compare): Add veccmpfx.
+ * config/rs6000/a2.md (ppca2-fp): Add fpsimple.
+ * config/rs6000/cell.md (cell-fp): Add fpsimple.
+ (cell-vecsimple): Add veclogical, vecmove.
+ (cell-veccmp): Add veccmpfx.
+ * config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple.
+ * config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove,
+ veccmpfx.
+ * config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
+ * config/rs6000/power4.md (power4-fp): Add fpsimple.
+ (power4-vecsimple): Add veclogical, vecmove.
+ (power4-veccmp): Add veccmpfx.
+ * config/rs6000/power5.md (power5-fp): Add fpsimple.
+ * config/rs6000/power6.md (power6-fp): Add fpsimple.
+ (power6-vecsimple): Add veclogical, vecmove.
+ (power6-veccmp): Add veccmpfx.
+ * config/rs6000/power7.md (power7-fp): Add fpsimple.
+ (power7-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/power8.md (power8-fp): Add fpsimple.
+ (power8-vecsimple): Add veclogical, vecmove, veccmpfx.
+ * config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
+ * config/rs6000/titan.md (titan_fp): Add fpsimple.
+ * config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
+ fpsimple.
+ * config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.
+
2016-06-27 Peter Bergner <bergner@vnet.ibm.com>
PR target/71656
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
- (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
+ (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
ppc476_f_pipe+ppc476_i_pipe")
(define_insn_reservation "ppc476-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe")
"(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601")
(define_insn_reservation "ppc601-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601")
"(fpu_603+iu_603*2),bpu_603")
(define_insn_reservation "ppc603-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc603"))
"fpu_603")
"fpu_6xx")
(define_insn_reservation "ppc604-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
"ppc7450_du,fpu_7450")
(define_insn_reservation "ppc7450-fp" 5
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
;; Altivec
(define_insn_reservation "ppc7450-vecsimple" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-veccmp" 2
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
;; Altivec
(define_insn_reservation "ppc7400-vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; D.8.1
(define_insn_reservation "ppca2-fp" 6
- (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppca2"))
"axu")
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*")
+ [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*")
(set_attr "length" "4,4,4,20,20,20,4,8,32")])
;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
default: gcc_unreachable ();
}
}
- [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
+ [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")])
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpequ<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_gt<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgts<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_gtu<mode>"
[(set (match_operand:VI2 0 "altivec_register_operand" "=v")
(match_operand:VI2 2 "altivec_register_operand" "v")))]
"<VI_unit>"
"vcmpgtu<VI_char> %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_eqv4sf"
[(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*altivec_vsel<mode>_uns"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Fused multiply add.
(match_dup 2)))]
"<VI_unit>"
"vcmpequ<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgts<VI_char>_p"
[(set (reg:CC 74)
(match_dup 2)))]
"<VI_unit>"
"vcmpgts<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgtu<VI_char>_p"
[(set (reg:CC 74)
(match_dup 2)))]
"<VI_unit>"
"vcmpgtu<VI_char>. %0,%1,%2"
- [(set_attr "type" "veccmp")])
+ [(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpeqfp_p"
[(set (reg:CC 74)
; Basic FP latency is 10 cycles, thoughput is 1/cycle
(define_insn_reservation "cell-fp" 10
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*8")
; VMX
(define_insn_reservation "cell-vecsimple" 4
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
;; TODO: add support for recording instructions
(define_insn_reservation "cell-veccmp" 4
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_expand "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_expand "abstd2"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_insn "*nabstd2_fpr"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
;; Hardware support for decimal floating point operations.
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fp" 3
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
;; VSFX.
(define_insn_reservation "e6500_vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
"fpu_mpc,bpu_mpc")
(define_insn_reservation "mpccore-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*2")
; Basic FP latency is 6 cycles
(define_insn_reservation "power4-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power4"))
"fpq_power4")
; VMX
(define_insn_reservation "power4-vecsimple" 2
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power4"))
"vq_power4")
; vecfp compare
(define_insn_reservation "power4-veccmp" 8
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power4"))
"vq_power4")
; Basic FP latency is 6 cycles
(define_insn_reservation "power5-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power5"))
"fpq_power5")
(define_bypass 9 "power6-mtcr" "power6-branch")
(define_insn_reservation "power6-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power6"))
"FPU_power6")
"LSF_power6")
(define_insn_reservation "power6-vecsimple" 3
- (and (eq_attr "type" "vecsimple")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
(define_insn_reservation "power6-veccmp" 1
- (and (eq_attr "type" "veccmp")
+ (and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power6"))
"FPU_power6")
; VS Unit (includes FP/VSX/VMX/DFP)
(define_insn_reservation "power7-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
"DU_power7,VSU_power7")
(define_insn_reservation "power7-vecsimple" 2
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
(define_insn_reservation "power8-fp" 6
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecsimple" 2
- (and (eq_attr "type" "vecperm,vecsimple,veccmp")
+ (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp,
+ veccmpfx")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
switch (attr_type)
{
case TYPE_FP:
- if (get_attr_type (dep_insn) == TYPE_FP)
+ case TYPE_FPSIMPLE:
+ if (get_attr_type (dep_insn) == TYPE_FP
+ || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
return 1;
break;
case TYPE_FPLOAD:
brinc,
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
+ veclogical,veccmpfx,vecexts,vecmove,
htm"
(const_string "integer"))
"@
fabs %0,%1
xsabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "*nabs<mode>2_fpr"
"@
fnabs %0,%1
xsnabsdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "neg<mode>2"
"@
fneg %0,%1
xsnegdp %x0,%x1"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "add<mode>3"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")])
+ [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")])
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
;; fsel instruction and some auxiliary computations. Then we just have a
(match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
"TARGET_P9_MINMAX"
"xxsel %x0,%x1,%x3,%x4"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
\f
;; Conversions to and from floating-point.
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
[(set (attr "type")
(if_then_else
(match_test "vsx_register_operand (operands[0], <MODE>mode)")
- (const_string "vecsimple")
+ (const_string "veclogical")
(const_string "integer")))
(set (attr "length")
(if_then_else
mt%0 %1
mf%1 %0
nop"
- [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
+ [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat"
#
#
#"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
(define_insn "*mov<mode>_softfloat32"
mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
- [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+ [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
(set_attr "length" "4")])
(define_insn "*mov<mode>_softfloat64"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "trunc<mode>df2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
else
return \"fneg %0,%1\;fneg %L0,%L1\";
}"
- [(set_attr "type" "fp")
+ [(set_attr "type" "fpsimple")
(set_attr "length" "8")])
(define_expand "abs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlxor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; IEEE 128-bit absolute value
(define_insn_and_split "ieee_128bit_vsx_abs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlandc %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; IEEE 128-bit negative absolute value
(define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2"
(use (match_operand:V16QI 2 "register_operand" "v"))]
"TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
"xxlor %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "veclogical")])
;; Float128 conversion functions. These expand to library function calls.
;; We use expand to convert from IBM double double to IEEE 128-bit
UNSPEC_P8V_FMRGOW))]
"!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"fmrgow %0,%1,%2"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "fpsimple")])
(define_insn "p8_mtvsrwz"
[(set (match_operand:DF 0 "register_operand" "=d")
#
#"
[(set_attr "type"
- "store, load, *, fpstore, fpload, fp,
- *, fpstore, fpstore, fpload, fpload, vecsimple,
- vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple,
+ "store, load, *, fpstore, fpload, fpsimple,
+ *, fpstore, fpstore, fpload, fpload, veclogical,
+ vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple,
vecsimple")])
(define_split
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
- "store, load, *, *, *, *,
- fpstore, fpload, fp, fpstore, fpstore, fpload,
- fpload, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple,
- vecsimple, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
- mftgpr, mffgpr, mftgpr, mffgpr")
+ "store, load, *, *, *, *,
+ fpstore, fpload, fpsimple, fpstore, fpstore, fpload,
+ fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,
+ veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
+ mftgpr, mffgpr, mftgpr, mffgpr")
(set_attr "length"
"4, 4, 4, 4, 4, 20,
operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
}
- [(set_attr "type" "fp,fp")
+ [(set_attr "type" "fpsimple,fp")
(set_attr "length" "4,8")])
(define_insn "unpack<mode>"
UNSPEC_COPYSIGN))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscpsgnqp %0,%2,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecmove")])
(define_insn "copysign<mode>3_soft"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnegqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
(define_insn "abs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
(define_insn "*nabs<mode>2_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnabsqp %0,%1"
- [(set_attr "type" "vecfloat")])
+ [(set_attr "type" "vecmove")])
;; Initially don't worry about doing fusion
(define_insn "*fma<mode>4_hw"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,veclogical")
(set_attr "length" "0,4")])
(define_insn_and_split "trunctfkf2"
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "*,vecsimple")
+ [(set_attr "type" "*,veclogical")
(set_attr "length" "0,4")])
(define_insn "trunc<mode>df2_hw"
mfvsrd %0,%x1
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mftgpr,fpstore,vecsimple")])
+ [(set_attr "type" "mftgpr,fpstore,veclogical")])
(define_insn "*ieee128_mfvsrd_32bit"
"@
stxsdx %x1,%y0
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpstore,vecsimple")])
+ [(set_attr "type" "fpstore,veclogical")])
(define_insn "*ieee128_mfvsrwz"
[(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")
mtvsrd %x0,%1
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "mffgpr,fpload,vecsimple")])
+ [(set_attr "type" "mffgpr,fpload,veclogical")])
(define_insn "*ieee128_mtvsrd_32bit"
[(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v")
"@
lxsdx %x0,%y1
xxlor %x0,%x1,%x1"
- [(set_attr "type" "fpload,vecsimple")])
+ [(set_attr "type" "fpload,veclogical")])
;; IEEE 128-bit instructions with round to odd semantics
(define_insn "*trunc<mode>df2_odd"
"mciu_rs64,fpu_rs64,bpu_rs64")
(define_insn_reservation "rs64a-fp" 4
- (and (eq_attr "type" "fp,dmul")
+ (and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64")
;; Make sure the "titan_fp" rule stays last, as it's a catch all for
;; double-precision and unclassified (e.g. fsel) FP-instructions
(define_insn_reservation "titan_fp" 10
- (and (eq_attr "type" "fpcompare,fp,dmul")
+ (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
}
}
[(set_attr "length" "0,4")
- (set_attr "type" "vecsimple")])
+ (set_attr "type" "veclogical")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
(define_insn "*vsx_xxsel<mode>_uns"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecmove")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
else
gcc_unreachable ();
}
- [(set_attr "type" "vecsimple,mftgpr,mftgpr,vecperm")])
+ [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")])
;; Optimize extracting a single scalar element from memory if the scalar is in
;; the correct location to use a single load.
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsb2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
(define_insn "vsx_sign_extend_hi_<mode>"
[(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v")
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsh2<wd> %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
(define_insn "*vsx_sign_extend_si_v2di"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v")
UNSPEC_VSX_SIGN_EXTEND))]
"TARGET_P9_VECTOR"
"vextsw2d %0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecexts")])
\f
;; ISA 3.0 memory operations
(define_insn_reservation "fp-default" 2
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_default"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2")
(define_insn_reservation "fp-addsub-s" 14
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_s"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
(define_insn_reservation "fp-addsub-d" 18
(and (and
- (eq_attr "type" "fp")
+ (eq_attr "type" "fp,fpsimple")
(eq_attr "fp_type" "fp_addsub_d"))
(eq_attr "cpu" "ppc405"))
"Xfpu_issue*2,Xfpu_addsub")
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