radeonsi/gfx10: set the DCC constant encoding flag

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 91b474d4d8f7acb89c997837dddafd6391c84962..e25c65abda887ef2d58cc5aed66fc47538955945 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1124,7 +1124,8 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                                           sscreen->info.family == CHIP_RAVEN;
        sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
                                        sscreen->info.family == CHIP_RAVEN;
-       sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
+       sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
+                                          sscreen->info.chip_class >= GFX10;
 
        /* Only enable primitive binning on APUs by default. */
        sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||