remove repeated section,

put one-liner explaining what SVP64 is
(which will be understood by IBM)

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 806fccf854b94db29fad2957ba7b624d860042a9..f81893585a9306b81a275d3b549ff6b29c1c65d7 100644 (file)
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -151,6 +151,8 @@ VPU, 3D?).  Includes features normally found only on Cray-style Supercomputers
 (Cray-1, NEC SX-Aurora) and GPUs.  Keeps to a strict uniform RISC paradigm,
 leveraging a scalar ISA by using "Prefixing".
 \textbf{No dedicated vector opcodes exist in SV, at all}.
+SVP64 uses 25\% of the Power ISA v3.1 64-bit Prefix space (EXT001) to create
+the SV Vectorisation Context for the 32-bit Scalar Suffix.
 
 \vspace{10pt}
 Main design principles
@@ -193,15 +195,3 @@ Advantages include:
           ISAs. No more separate vector instructions.
 \end{itemize}
 
-\subsubsection{Prefix 64 - SVP64}
-
-SVP64, is a specification designed to solve the problems caused by
-SIMD implementations by:
-\begin{itemize}
-       \item Simplifying the hardware design
-       \item Reducing maintenance overhead
-       \item Reducing code size and power consumption
-       \item Easier for compilers, coders, documentation
-       \item Time to support platform is a fraction of conventional SIMD
-             (Less money on R\&D, faster to deliver)
-\end{itemize}