param_signed:
        TOK_SIGNED {
                astbuf1->is_signed = true;
+       } | TOK_UNSIGNED {
+               astbuf1->is_signed = false;
        } | /* empty */;
 
 param_integer:
                astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
                astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
                astbuf1->is_signed = true;
-       } | /* empty */;
+       }
 
 param_real:
        TOK_REAL {
                if (astbuf1->children.size() != 1)
                        frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
                astbuf1->children.push_back(new AstNode(AST_REALVALUE));
-       } | /* empty */;
+       }
 
 param_range:
        range {
                }
        };
 
+param_integer_type: param_integer param_signed
+param_range_type: type_vec param_signed param_range
+param_implicit_type: param_signed param_range
+
 param_type:
-       param_signed param_integer param_real param_range |
+       param_integer_type | param_real | param_range_type | param_implicit_type |
        hierarchical_type_id {
                astbuf1->is_custom_type = true;
                astbuf1->children.push_back(new AstNode(AST_WIRETYPE));