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Merge pull request #181 from rubund/input_logic_allowed
authorClifford Wolf <clifford@clifford.at>
Tue, 21 Jun 2016 06:44:20 +0000 (08:44 +0200)
committerGitHub <noreply@github.com>
Tue, 21 Jun 2016 06:44:20 +0000 (08:44 +0200)
Allow defining input ports as "input logic" in SystemVerilog


Trivial merge