cannot replace lowercase "kind" with "type" as it is a python keyword.
have to think of a better (*short*) argument name
from openpower.consts import DEFAULT_MSR
from openpower.fpscr import FPSCRState
from openpower.xer import XERState
-from openpower.util import LogKind, log
+from openpower.util import LogType, log
LDST_UPDATE_INSNS = ['ldu', 'lwzu', 'lbzu', 'lhzu', 'lhau', 'lfsu', 'lfdu',
'stwu', 'stbu', 'sthu', 'stfsu', 'stfdu', 'stdu',
misaligned_ok=True)
self.imem = self.mem
self.mem.initialize(row_bytes=4, initial_mem=initial_insns)
- self.mem.log_fancy(kind=LogKind.InstrInOuts)
+ self.mem.log_fancy(kind=LogType.InstrInOuts)
else:
self.mem = Mem(row_bytes=8, initial_mem=initial_mem,
misaligned_ok=True)
- self.mem.log_fancy(kind=LogKind.InstrInOuts)
+ self.mem.log_fancy(kind=LogType.InstrInOuts)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
# MMU mode, redirect underlying Mem through RADIX
if mmu:
self.spr['XER'][XER_bits['OV']] = ov
self.spr['XER'][XER_bits['OV32']] = ov32
log(f"write OV/OV32 OV={ov} OV32={ov32}",
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
else:
# TODO: if 32-bit mode, set ca to ca32
self.spr['XER'][XER_bits['CA']] = ca
self.spr['XER'][XER_bits['CA32']] = ca32
log(f"write CA/CA32 CA={ca} CA32={ca32}",
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
return
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
# see http://bugs.libre-riscv.org/show_bug.cgi?id=282
asmop = yield from self.get_assembly_name()
log("call", ins_name, asmop,
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
# sv.setvl is *not* a loop-function. sigh
log("is_svp64_mode", self.is_svp64_mode, asmop)
if self.is_svp64_mode and vl == 0:
self.pc.update(self.namespace, self.is_svp64_mode)
log("SVP64: VL=0, end of call", self.namespace['CIA'],
- self.namespace['NIA'], kind=LogKind.InstrInOuts)
+ self.namespace['NIA'], kind=LogType.InstrInOuts)
return
# for when SVREMAP is active, using pre-arranged schedule.
if name in fregs:
reg_val = SelectableInt(self.fpr(base, is_vec, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value),
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
self.trace("r:FPR:%d:%d:%d " % (base, offs, ew_src))
elif name is not None:
reg_val = SelectableInt(self.gpr(base, is_vec, offs, ew_src))
self.trace("r:GPR:%d:%d:%d " % (base, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value),
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
reg_val = SelectableInt(0, ew_src)
if name in info.special_regs:
log('writing special %s' % name, output, special_sprs)
log("write reg %s 0x%x" % (name, output.value),
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
if name in special_sprs:
self.spr[name] = output
else:
output = SelectableInt(0, EFFECTIVELY_UNLIMITED)
log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
output.value, ew_dst),
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
# zero-extend tov64 bit begore storing (should use EXT oh well)
if output.bits > 64:
output = SelectableInt(output.value, 64)
from collections import defaultdict
from openpower.decoder.selectable_int import SelectableInt
-from openpower.util import log, LogKind
+from openpower.util import log, LogType
import math
import enum
from cached_property import cached_property
print("%016x: %016x" % ((k*8) & 0xffffffffffffffff, v), s)
return res
- def log_fancy(self, *, kind=LogKind.Default, name="Memory",
+ def log_fancy(self, *, kind=LogType.Default, name="Memory",
log2_line_size=4, log2_column_chunk_size=3, log=log):
line_size = 1 << log2_line_size
subline_mask = line_size - 1
from pathlib import Path
from nmutil.plain_data import plain_data
-from openpower.util import LogKind
+from openpower.util import LogType
RAINBOW_SMILEY = Path(__file__).with_name("rainbow_smiley.jpg").read_bytes()
mem = Mem()
for i, b in enumerate(mem_bytes):
mem.st(0x10000000 + i, b, 1)
- mem.log_fancy(log=lambda *args, kind=LogKind.Default, **kwargs:
+ mem.log_fancy(log=lambda *args, kind=LogType.Default, **kwargs:
print(*args, **kwargs))
import os
from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
-from openpower.util import LogKind, log, \
+from openpower.util import LogType, log, \
fast_reg_to_spr, slow_reg_to_spr # HACK!
from openpower.consts import XERRegsEnum, DEFAULT_MSR
# TODO(programmerjake): translate to final test sending
# skip signal to unittest. for now, just print the skipped
# reason and ignore
- log(f"SKIPPED({n}):", str(e), kind=LogKind.SkipCase)
+ log(f"SKIPPED({n}):", str(e), kind=LogType.SkipCase)
@contextmanager
def subTest(self, **kwargs):
from openpower.test.wb_get import wb_get
import openpower.test.wb_get as wbget
from openpower.test.state import TestState, StateRunner, ExpectedState
-from openpower.util import log, LogKind
+from openpower.util import log, LogType
class SimRunner(StateRunner):
# extra new-line so it's easier to visually separate each
# instruction in output
log(f"\n0x{sim.pc.CIA.value:04X}: {ins % (1 << 32):08X} {code}",
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
log("sim instr: 0x{:X} pc=0x{:X}".format(ins & 0xffffffff,
sim.pc.CIA.value))
state = yield from TestState("sim", sim, dut, code)
sim_states.append(state)
- log(f"final pc: 0x{sim.pc.CIA.value:X}", kind=LogKind.InstrInOuts)
+ log(f"final pc: 0x{sim.pc.CIA.value:X}", kind=LogType.InstrInOuts)
if self.dut.allow_overlap:
# get last state, at end of run
yield from runner.prepare_for_test(test)
log("running test: ", test.name, test.subtest_args,
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
program = test.program
def format_regs(regs):
out.append(f"r{i} = 0x{v:X} {values}")
return "\n".join(out)
log("regs:", format_regs(test.regs),
- kind=LogKind.InstrInOuts)
- log("sprs", test.sprs, kind=LogKind.InstrInOuts)
- log("cr", test.cr, kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
+ log("sprs", test.sprs, kind=LogType.InstrInOuts)
+ log("cr", test.cr, kind=LogType.InstrInOuts)
log("mem", test.mem)
- log("msr", test.msr, kind=LogKind.InstrInOuts)
+ log("msr", test.msr, kind=LogType.InstrInOuts)
def format_assembly(assembly):
# type: (str) -> str
pc += 4
return "\n".join(out)
log("assembly:\n" + format_assembly(program.assembly),
- kind=LogKind.InstrInOuts)
+ kind=LogType.InstrInOuts)
gen = list(program.generate_instructions())
insncode = program.assembly.splitlines()
instructions = list(zip(gen, insncode))
return random.randint(min_val, (1 << logrange)-1)
-class LogKind(Enum):
+class LogType(Enum):
Default = "default"
InstrInOuts = "instr_in_outs"
SkipCase = "skip_case"
@lru_cache(typed=True)
def __parse_log_env_var(silencelog_raw):
if silencelog_raw is None:
- return {k: False for k in LogKind}
+ return {k: False for k in LogType}
silencelog = os.environ.decodevalue(silencelog_raw)
silencelog = silencelog.lower().split(",")
for i, v in enumerate(silencelog):
silencelog[i] = v.strip()
- retval = {k: True for k in LogKind}
+ retval = {k: True for k in LogType}
if len(silencelog) > 1 and silencelog[-1] == "":
# allow trailing comma
silencelog.pop()
if len(silencelog) == 1:
if silencelog[0] in ("0", "false"):
- for k in LogKind:
+ for k in LogType:
retval[k] = False
silencelog.pop()
if silencelog[0] in ("1", "true", ""):
v = v[1:]
silenced = False
matches = False
- for k in LogKind:
+ for k in LogType:
if fnmatchcase(k.value, v):
matches = True
retval[k] = silenced
- assert matches, (f"SILENCELOG: {v!r} did not match any known LogKind: "
- f"LogKinds: {' '.join(i.value for i in LogKind)}")
+ assert matches, (f"SILENCELOG: {v!r} did not match any known LogType: "
+ f"LogTypes: {' '.join(i.value for i in LogType)}")
# for k, v in retval.items():
# print(repr(k), "silenced" if v else "active")
return retval
__ENCODED_SILENCELOG = os.environ.encodekey("SILENCELOG")
-def log(*args, kind=LogKind.Default, **kwargs):
+def log(*args, kind=LogType.Default, **kwargs):
"""verbose printing, can be disabled by setting env var "SILENCELOG".
"""
# look up in os.environ._data since it is a dict and hence won't raise
projects / openpower-isa.git / commitdiff